memory.h File Reference

Constants for areas of the system memory map. More...

#include <sys/cdefs.h>

Go to the source code of this file.

Macros
#define	MEM_AREA_CACHE_MASK   0x1fffffff
	Mask a cache-agnostic address.
#define	MEM_AREA_U0_BASE   0x00000000
	U0 memory region base (cacheable).
#define	MEM_AREA_P0_BASE   0x00000000
	P0 memory region base (cacheable).
#define	MEM_AREA_P1_BASE   0x80000000
	P1 memory region base (cacheable).
#define	MEM_AREA_P2_BASE   0xa0000000
	P2 memory region base (non-cacheable).
#define	MEM_AREA_P3_BASE   0xc0000000
	P3 memory region base (cacheable).
#define	MEM_AREA_P4_BASE   0xe0000000
	P4 memory region base (non-cacheable)
#define	MEM_AREA_SQ_BASE   0xe0000000
	Store Queue (SQ) memory base.
#define	MEM_AREA_ICACHE_ADDRESS_ARRAY_BASE   0xf0000000
	Instruction cache address array base.
#define	MEM_AREA_ICACHE_DATA_ARRAY_BASE   0xf1000000
	Instruction cache data array base.
#define	MEM_AREA_ITLB_ADDRESS_ARRAY_BASE   0xf2000000
	Instruction TLB address array base.
#define	MEM_AREA_ITLB_DATA_ARRAY1_BASE   0xf3000000
	Instruction TLB data array 1 base.
#define	MEM_AREA_ITLB_DATA_ARRAY2_BASE   0xf3800000
	Instruction TLB data array 2 base.
#define	MEM_AREA_OCACHE_ADDRESS_ARRAY_BASE   0xf4000000
	Operand cache address array base.
#define	MEM_AREA_OCACHE_DATA_ARRAY_BASE   0xf5000000
	Instruction cache data array base.
#define	MEM_AREA_UTLB_ADDRESS_ARRAY_BASE   0xf6000000
	Unified TLB address array base.
#define	MEM_AREA_UTLB_DATA_ARRAY1_BASE   0xf7000000
	Unified TLB data array 1 base.
#define	MEM_AREA_UTLB_DATA_ARRAY2_BASE   0xf7800000
	Unified TLB data array 2 base.
#define	MEM_AREA_CTRL_REG_BASE   0xff000000
	Control Register base.
#define	SH4_REG_MMU_PTEH   0xff000000
	MMU Page table entry high.
#define	SH4_REG_MMU_PTEL   0xff000004
	MMU Page table entry low.
#define	SH4_REG_MMU_TTB   0xff000008
	MMU Translation table base.
#define	SH4_REG_MMU_TEA   0xff00000c
	MMU TLB Exception address.
#define	SH4_REG_MMU_CR   0xff000010
	MMU Control Register.
#define	SH4_REG_MMU_PTEA   0xff000034
	MMU Page table entry assistance.
#define	SH4_REG_UBC_BASRA   0xff000014
	UBC Break ASID register A.
#define	SH4_REG_UBC_BASRB   0xff000018
	UBC Break ASID register B.
#define	SH4_REG_UBC_BARA   0xff200000
	UBC Break address register A.
#define	SH4_REG_UBC_BAMRA   0xff200004
	UBC Break address mask register A.
#define	SH4_REG_UBC_BBRA   0xff200008
	UBC Break bus cycle register A.
#define	SH4_REG_UBC_BARB   0xff20000c
	UBC Break address register B.
#define	SH4_REG_UBC_BAMRB   0xff200010
	UBC Break address mask register B.
#define	SH4_REG_UBC_BBRB   0xff200014
	UBC Break bus cycle register B.
#define	SH4_REG_UBC_BDRB   0xff200018
	UBC Break data register B.
#define	SH4_REG_UBC_BDMRB   0xff20001c
	UBC Break mask register B.
#define	SH4_REG_UBC_BRCR   0xff200020
	UBC Break control register.

Detailed Description

Constants for areas of the system memory map.

Various addresses and masks that are set by the SH7750. None of the values here are Dreamcast-specific.

These values are drawn from the Hitatchi SH7750 Series Hardware Manual rev 6.0.

Author

Donald Haase