MMU Control Registers. More...

Macros
#define	SH4_REG_MMU_PTEH 0xff000000
	MMU Page table entry high.

#define	SH4_REG_MMU_PTEL 0xff000004
	MMU Page table entry low.

#define	SH4_REG_MMU_TTB 0xff000008
	MMU Translation table base.

#define	SH4_REG_MMU_TEA 0xff00000c
	MMU TLB Exception address.

#define	SH4_REG_MMU_CR 0xff000010
	MMU Control Register.

#define	SH4_REG_MMU_PTEA 0xff000034
	MMU Page table entry assistance.

Detailed Description

MMU Control Registers.

See also: arch\mmu.h

These are registers for controlling the MMU as defined in table 3.1 of Hitatchi SH7750 Series Hardware Manual rev 6.0, titled "MMU Registers". All are accessed as 32-bit values.

Macro Definition Documentation

◆ SH4_REG_MMU_CR

#define SH4_REG_MMU_CR 0xff000010

MMU Control Register.

Holds configuration values including enable/disable of MMU Address Translation (at bit 0)

◆ SH4_REG_MMU_PTEA

#define SH4_REG_MMU_PTEA 0xff000034

MMU Page table entry assistance.

Stores assistance bits for PCMCIA access to the UTLB via LDTLB. This is currently unused by KOS.

◆ SH4_REG_MMU_PTEH

#define SH4_REG_MMU_PTEH 0xff000000

MMU Page table entry high.

When an MMU exception or address error exception occurs, the virtual page number (VPN) (the upper 22-bits of the virtual address causing the exception) is written to the register. The bottom 8 bits of the register are software-fillable as an 8 bit ID (ASID) of the process causing the exception.

◆ SH4_REG_MMU_PTEL

#define SH4_REG_MMU_PTEL 0xff000004

MMU Page table entry low.

Holds the physical page number (PPN) in bits 10-28 and page management flags in 0-8.

◆ SH4_REG_MMU_TEA

#define SH4_REG_MMU_TEA 0xff00000c

MMU TLB Exception address.

After an MMU exception or address error exception occurs, the virtual address where the exception occurred is stored here.

◆ SH4_REG_MMU_TTB

#define SH4_REG_MMU_TTB 0xff000008

MMU Translation table base.

Holds the base address of the currently used page table.

Macros