UBC

UBC Control Registers. More...

Macros
#define	SH4_REG_UBC_BASRA   0xff000014
	UBC Break ASID register A.
#define	SH4_REG_UBC_BASRB   0xff000018
	UBC Break ASID register B.
#define	SH4_REG_UBC_BARA   0xff200000
	UBC Break address register A.
#define	SH4_REG_UBC_BAMRA   0xff200004
	UBC Break address mask register A.
#define	SH4_REG_UBC_BBRA   0xff200008
	UBC Break bus cycle register A.
#define	SH4_REG_UBC_BARB   0xff20000c
	UBC Break address register B.
#define	SH4_REG_UBC_BAMRB   0xff200010
	UBC Break address mask register B.
#define	SH4_REG_UBC_BBRB   0xff200014
	UBC Break bus cycle register B.
#define	SH4_REG_UBC_BDRB   0xff200018
	UBC Break data register B.
#define	SH4_REG_UBC_BDMRB   0xff20001c
	UBC Break mask register B.
#define	SH4_REG_UBC_BRCR   0xff200020
	UBC Break control register.

Detailed Description

UBC Control Registers.

See also

dc\ubc.h

These are registers for controlling the UBC as defined in table 20.1 of Hitatchi SH7750 Series Hardware Manual rev 6.0, titled "UBC Registers"

Macro Definition Documentation

SH4_REG_UBC_BAMRA

#define SH4_REG_UBC_BAMRA   0xff200004

UBC Break address mask register A.

Specifies the settings for masking the ASID in channel A. 8-bit RW.

SH4_REG_UBC_BAMRB

#define SH4_REG_UBC_BAMRB   0xff200010

UBC Break address mask register B.

Specifies the settings for masking the ASID in channel B. 8-bit RW.

SH4_REG_UBC_BARA

#define SH4_REG_UBC_BARA   0xff200000

UBC Break address register A.

Specifies the virtual address used in the channel A break conditions. 32-bit RW.

SH4_REG_UBC_BARB

#define SH4_REG_UBC_BARB   0xff20000c

UBC Break address register B.

Specifies the virtual address used in the channel B break conditions. 32-bit RW.

SH4_REG_UBC_BASRA

#define SH4_REG_UBC_BASRA   0xff000014

UBC Break ASID register A.

Specifies the ASID used in the channel A break condition. 8-bit RW.

SH4_REG_UBC_BASRB

#define SH4_REG_UBC_BASRB   0xff000018

UBC Break ASID register B.

Specifies the ASID used in the channel B break condition. 8-bit RW.

SH4_REG_UBC_BBRA

#define SH4_REG_UBC_BBRA   0xff200008

UBC Break bus cycle register A.

Sets three conditions: 1) instruction/operand access 2) RW 3) Operand size. 16-bit RW.

SH4_REG_UBC_BBRB

#define SH4_REG_UBC_BBRB   0xff200014

UBC Break bus cycle register B.

Sets three conditions: 1) instruction/operand access 2) RW 3) Operand size. 16-bit RW.

SH4_REG_UBC_BDMRB

#define SH4_REG_UBC_BDMRB   0xff20001c

UBC Break mask register B.

Specifies which bits of the break data set in SH4_REG_UBC_BDRB are to be masked. 32-bit RW. Currently unused by KOS

SH4_REG_UBC_BDRB

#define SH4_REG_UBC_BDRB   0xff200018

UBC Break data register B.

Specifies the data to be used in the channel B break conditions. 32-bit RW. Currently unused by KOS

SH4_REG_UBC_BRCR

#define SH4_REG_UBC_BRCR   0xff200020

UBC Break control register.

Specifies various settings for UBC as well as condition match flags. 16-bit RW.