cache.h File Reference

Cache management functionality. More...

#include <kos/cdefs.h>
#include <kos/regfield.h>
#include <stdbool.h>
#include <stdint.h>

Go to the source code of this file.

Macros
#define	CCR_OCE   BIT(0) /** < OC enable */
#define	CCR_WT   BIT(1) /** < Write-through enable (for P0/U0/P3 in non-MMU mode) */
#define	CCR_CB   BIT(2) /** < Copy-back enable for P1 area */
#define	CCR_OCI   BIT(3) /** < OC invalidate */
#define	CCR_ORA   BIT(5) /** < OC RAM enable */
#define	CCR_OIX   BIT(7) /** < OC INDEX enable */
#define	CCR_ICE   BIT(8) /** < IC enable (in non-MMU mode) */
#define	CCR_ICI   BIT(11) /** < IC invalidate */
#define	CCR_IIX   BIT(15) /** < IC INDEX enable */
#define	CCR_DEFAULT   (CCR_ICI | CCR_ICE | CCR_OCI | CCR_CB | CCR_OCE)
	Default cache settings.
#define	__ocram   __attribute__((section(".ocram")))
	Mark a variable as residing in OCRAM.

Functions
void	cache_write_ccr (uint32_t mask, uint32_t value)
	Write CCR register.
static void	dcache_toggle_ocindex (bool enable)
	Enable or disable OCINDEX mode.
static void	dcache_toggle_ocram (bool enable)
	Enable or disable OCRAM mode.
static void	icache_toggle_icindex (bool enable)
	Enable or disable ICINDEX mode.

Detailed Description

Cache management functionality.

This file contains definitions and low-level routines to manipulate the instruction and data caches.

Author

Paul Cercueil

Matt Slevinsky

TapamN

Macro Definition Documentation

__ocram

#define __ocram   __attribute__((section(".ocram")))

Mark a variable as residing in OCRAM.

This can be used to place a variable in OCRAM space. Before any access (read or write) can be made, OCRAM needs to be enabled. Also note that after enabling OCRAM the variable will contain garbage, so the code must not rely on the content of the variable, and must not be statically initialized (even to zero).

Example: __ocram static uint32_t my_array[16];

CCR_CB

#define CCR_CB   BIT(2) /** < Copy-back enable for P1 area */

CCR_DEFAULT

#define CCR_DEFAULT   (CCR_ICI | CCR_ICE | CCR_OCI | CCR_CB | CCR_OCE)

Default cache settings.

CCR_ICE

#define CCR_ICE   BIT(8) /** < IC enable (in non-MMU mode) */

CCR_ICI

#define CCR_ICI   BIT(11) /** < IC invalidate */

Referenced by icache_toggle_icindex().

CCR_IIX

#define CCR_IIX   BIT(15) /** < IC INDEX enable */

Referenced by icache_toggle_icindex().

CCR_OCE

#define CCR_OCE   BIT(0) /** < OC enable */

CCR_OCI

#define CCR_OCI   BIT(3) /** < OC invalidate */

CCR_OIX

#define CCR_OIX   BIT(7) /** < OC INDEX enable */

Referenced by dcache_toggle_ocindex().

CCR_ORA

#define CCR_ORA   BIT(5) /** < OC RAM enable */

Referenced by dcache_toggle_ocram().

CCR_WT

#define CCR_WT   BIT(1) /** < Write-through enable (for P0/U0/P3 in non-MMU mode) */

Function Documentation

cache_write_ccr()

void cache_write_ccr	(	uint32_t	mask,
		uint32_t	value )

Write CCR register.

This function is used internally to write the cache control register.

Parameters

mask	Mask of the bits to update
value	Value to replace the masked bits with

Referenced by dcache_toggle_ocindex(), dcache_toggle_ocram(), and icache_toggle_icindex().

dcache_toggle_ocindex()

static void dcache_toggle_ocindex ( bool enable )

inlinestatic

Enable or disable OCINDEX mode.

This function can be used to enable or disable OCINDEX mode.

In OCINDEX mode, the bits 25 and 12-5 are used as the data cache line index. In non-OCINDEX mode, the bits 13-5 are used as the data cache line index.

Using OCINDEX, data memory-mapped to an address with bit 25 set (e.g. 0x2000000) will always stay in cache (unless its cache line is reused by another address with bit 25 set), as the RAM size on supported SH4 platforms is lower than (1 << 25), meaning that for common RAM addresses, bit 25 is always cleared.

Parameters

enable

Whether or not to enable OCINDEX mode

References cache_write_ccr(), and CCR_OIX.

dcache_toggle_ocram()

static void dcache_toggle_ocram ( bool enable )

inlinestatic

Enable or disable OCRAM mode.

This function can be used to enable or disable OCRAM mode.

In OCRAM mode, half the cache can be used as a scratchpad.

In OCRAM mode, the bits 13 and 11-5 are used as the cache line index. In non-OCRAM mode, the bits 13-5 are used as the cache line index.

Using OCRAM mode, the cache lines 128 to 255 and 384 to 511 are guaranteed to be unused, and can be accessed directly as if it was RAM. The 8 KiB scratchpad can then be accessed at address 0x7c001000, or preferably through any variable tagged with the __ocram tag.

Parameters

enable

Whether or not to enable OCINDEX mode

References cache_write_ccr(), and CCR_ORA.

icache_toggle_icindex()

static void icache_toggle_icindex ( bool enable )

inlinestatic

Enable or disable ICINDEX mode.

This function can be used to enable or disable ICINDEX mode.

In ICINDEX mode, the bits 25 and 11-5 are used as the instruction cache line index. In non-ICINDEX mode, the bits 12-5 are used as the instruction cache line index.

Using ICINDEX, code memory-mapped to an address with bit 25 set (e.g. 0x2000000) will always stay in cache (unless its cache line is reused by another address with bit 25 set), as the RAM size on supported SH4 platforms is lower than (1 << 25), meaning that for common RAM addresses, bit 25 is always cleared.

Parameters

enable

Whether or not to enable ICINDEX mode

References cache_write_ccr(), CCR_ICI, and CCR_IIX.