PVR Driver Registers. More...

#include <kos/cdefs.h>
#include <arch/arch.h>

Macros
#define	PVR_GET(REG)
	Retrieve a PVR register value.

#define	PVR_SET(REG, VALUE)
	Set a PVR register value.

#define	PVR2_ADDR_STRIDE 0x02000000
	Address stride from CLXA to CLXB (registers and VRAM windows).

#define	PVR2_GET(REG)
	Retrieve a register from the second PVR (CLXB).

#define	PVR2_SET(REG, VALUE)
	Set a register on the second PVR (CLXB).

#define	PVR_BCAST_SET(REG, VALUE)
	Write a PVR register to both chips (write-only broadcast).

#define	PVR_ID 0x0000
	Chip ID.

#define	PVR_REVISION 0x0004
	Chip revision.

#define	PVR_RESET 0x0008
	Reset pins.

#define	PVR_ISP_START 0x0014
	Start the ISP/TSP.

#define	PVR_TEST_SELECT 0x0018
	Test select (writes prohibited)

#define	PVR_ISP_VERTBUF_ADDR 0x0020
	Vertex buffer address for scene rendering.

#define	PVR_ISP_TILEMAT_ADDR 0x002c
	Tile matrix address for scene rendering.

#define	PVR_SPANSORT_CFG 0x0030
	Span sorter control – write 0x101 for now.

#define	PVR_BORDER_COLOR 0x0040
	Border Color in RGB888.

#define	PVR_FB_CFG_1 0x0044
	Framebuffer config 1.

#define	PVR_FB_CFG_2 0x0048
	Framebuffer config 2.

#define	PVR_RENDER_MODULO 0x004c
	Render modulo.

#define	PVR_FB_ADDR 0x0050
	Framebuffer start address.

#define	PVR_FB_IL_ADDR 0x0054
	Framebuffer odd-field start address for interlace.

#define	PVR_FB_SIZE 0x005c
	Framebuffer display size.

#define	PVR_RENDER_ADDR 0x0060
	Render output address.

#define	PVR_RENDER_ADDR_2 0x0064
	Output for strip-buffering.

#define	PVR_PCLIP_X 0x0068
	Horizontal clipping area.

#define	PVR_PCLIP_Y 0x006c
	Vertical clipping area.

#define	PVR_CHEAP_SHADOW 0x0074
	Cheap shadow control.

#define	PVR_OBJECT_CLIP 0x0078
	Distance for polygon culling.

#define	PVR_FPU_PARAM_CFG 0x007c
	Parameter read control – write 0x0027df77 for now.

#define	PVR_HALF_OFFSET 0x0080
	Pixel sampling control – write 7 for now.

#define	PVR_TEXTURE_CLIP 0x0084
	Distance for texture clipping.

#define	PVR_BGPLANE_Z 0x0088
	Distance for background plane.

#define	PVR_BGPLANE_CFG 0x008c
	Background plane config.

#define	PVR_ISP_FEED_CFG 0x0098
	Translucent polygon sort mode – write 0x00800408 for now.

#define	PVR_SDRAM_REFRESH 0x00a0
	Texture memory refresh counter – write 0x20 for now.

#define	PVR_SDRAM_ARB_CFG 0x00a4
	Texture memory arbiter control – write 0x1f on NAOMI.

#define	PVR_SDRAM_CFG 0x00a8
	Texture memory control – write 0x15d1c951 (DC) / 0x15d1c955 (NAOMI)

#define	PVR_FOG_TABLE_COLOR 0x00b0
	Table fog color.

#define	PVR_FOG_VERTEX_COLOR 0x00b4
	Vertex fog color.

#define	PVR_FOG_DENSITY 0x00b8
	Fog density coefficient.

#define	PVR_COLOR_CLAMP_MAX 0x00bc
	RGB Color clamp max.

#define	PVR_COLOR_CLAMP_MIN 0x00c0
	RGB Color clamp min.

#define	PVR_GUN_POS 0x00c4
	Light gun position.

#define	PVR_HPOS_IRQ 0x00c8
	Horizontal position IRQ.

#define	PVR_VPOS_IRQ 0x00cc
	Vertical position IRQ.

#define	PVR_IL_CFG 0x00d0
	Interlacing config.

#define	PVR_BORDER_X 0x00d4
	Window border X position.

#define	PVR_SCAN_CLK 0x00d8
	Clock and scanline values.

#define	PVR_BORDER_Y 0x00dc
	Window border Y position.

#define	PVR_TEXTURE_MODULO 0x00e4
	Output texture width modulo.

#define	PVR_VIDEO_CFG 0x00e8
	Misc video config.

#define	PVR_BITMAP_X 0x00ec
	Bitmap window X position.

#define	PVR_BITMAP_Y 0x00f0
	Bitmap window Y position.

#define	PVR_SCALER_CFG 0x00f4
	Smoothing scaler.

#define	PVR_PALETTE_CFG 0x0108
	Palette format.

#define	PVR_SYNC_STATUS 0x010c
	V/H blank status.

#define	PVR_FB_BURSTCTRL 0x0110
	Framebuffer burst control – write 0x93f39 for now.

#define	PVR_FB_C_SOF 0x0114
	Current framebuffer start address (read)

#define	PVR_Y_COEFF 0x0118
	Y scaling coefficient – write 0x8040 for now.

#define	PVR_PT_ALPHA_REF 0x011c
	Only pixels with alpha >= this value are drawn for Punch Through polygons.

#define	PVR_TA_OPB_START 0x0124
	Object Pointer Buffer start for TA usage.

#define	PVR_TA_VERTBUF_START 0x0128
	Vertex buffer start for TA usage.

#define	PVR_TA_OPB_END 0x012c
	OPB end for TA usage.

#define	PVR_TA_VERTBUF_END 0x0130
	Vertex buffer end for TA usage.

#define	PVR_TA_OPB_POS 0x0134
	Top used memory location in OPB for TA usage.

#define	PVR_TA_VERTBUF_POS 0x0138
	Top used memory location in vertbuf for TA usage.

#define	PVR_TILEMAT_CFG 0x013c
	Tile matrix size config.

#define	PVR_OPB_CFG 0x0140
	Active lists / list size.

#define	PVR_TA_INIT 0x0144
	Initialize vertex reg.

#define	PVR_YUV_ADDR 0x0148
	YUV conversion destination.

#define	PVR_YUV_CFG 0x014c
	YUV configuration.

#define	PVR_YUV_STAT 0x0150
	The number of YUV macroblocks converted.

#define	PVR_TA_LIST_CONT 0x0160
	TA list continuation.

#define	PVR_TA_OPB_INIT 0x0164
	Object pointer buffer position init.

#define	PVR_FOG_TABLE_BASE 0x0200
	Base of the fog table.

#define	PVR_PALETTE_TABLE_BASE 0x1000
	Base of the palette table.

#define	PVR_TA_INPUT 0x10000000
	TA command input (64-bit, TA)

#define	PVR_TA_YUV_CONV 0x10800000
	YUV converter (64-bit, TA)

#define	PVR_TA_TEX_MEM 0x11000000
	VRAM 64-bit, TA=>VRAM.

#define	PVR_TA_TEX_MEM_32 0x13000000
	VRAM 32-bit, TA->VRAM.

#define	PVR_RAM_BASE_32_P0 0x05000000
	VRAM 32-bit, P0 area, PVR->VRAM.

#define	PVR_RAM_BASE_64_P0 0x04000000
	VRAM 64-bit, P0 area, PVR->VRAM.

#define	PVR_RAM_BASE 0xa5000000
	VRAM 32-bit, P2 area, PVR->VRAM.

#define	PVR_RAM_INT_BASE 0xa4000000
	VRAM 64-bit, P2 area, PVR->VRAM.

#define	PVR_RAM_SIZE_MB (hardware_sys_mode(NULL) == HW_TYPE_RETAIL ? 8 : 16)
	RAM size in MiB.

#define	PVR_RAM_SIZE (PVR_RAM_SIZE_MB10241024)
	RAM size in bytes.

#define	PVR_RAM_TOP (PVR_RAM_BASE + PVR_RAM_SIZE)
	Top of raw PVR RAM.

#define	PVR_RAM_INT_TOP (PVR_RAM_INT_BASE + PVR_RAM_SIZE)
	Top of int PVR RAM.

#define	PVR2_RAM_BASE_32_P0 (PVR_RAM_BASE_32_P0 + PVR2_ADDR_STRIDE)
	CLXB VRAM 32-bit, P0.

#define	PVR2_RAM_BASE_64_P0 (PVR_RAM_BASE_64_P0 + PVR2_ADDR_STRIDE)
	CLXB VRAM 64-bit, P0.

#define	PVR2_RAM_BASE (PVR_RAM_BASE + PVR2_ADDR_STRIDE)
	CLXB VRAM 32-bit, P2.

#define	PVR2_RAM_INT_BASE (PVR_RAM_INT_BASE + PVR2_ADDR_STRIDE)
	CLXB VRAM 64-bit, P2.

#define	PVR2_RAM_TOP (PVR2_RAM_BASE + PVR_RAM_SIZE)
	Top of CLXB 32-bit VRAM.

#define	PVR2_RAM_INT_TOP (PVR2_RAM_INT_BASE + PVR_RAM_SIZE)
	Top of CLXB 64-bit VRAM.

#define	PVR_RESET_ALL 0xffffffff
	Reset the whole PVR.

#define	PVR_RESET_NONE 0x00000000
	Cancel reset state.

#define	PVR_RESET_TA 0x00000001
	Reset only the TA.

#define	PVR_RESET_ISPTSP 0x00000002
	Reset only the ISP/TSP.

#define	PVR_ISP_START_GO 0xffffffff
	Write to the PVR_ISP_START register to start rendering.

#define	PVR_TA_INIT_GO 0x80000000
	Write to the PVR_TA_INIT register to confirm settings.

#define	PVR_TXR_STRIDE_MULT GENMASK(4, 0)
	Bottom 5 bits contain the size when using PVR_TXRFMT_X32_STRIDE.

#define	PVR_SCALER_CFG_FSAA BIT(16)
	Enable FSAA.

#define	PVR_SCALER_CFG_VSCALE_FACTOR GENMASK(15, 0)
	Vertical scale factor = 1024 / value.

Detailed Description

PVR Driver Registers.

This file provides the low-level driver implementation details for the PowerVR API, including its memory map and register accessors.

Author: Megan Potter; Roger Cattermole; Paul Boese; Brian Paul; Lawrence Sebald; Benoit Miller; Ruslan Rostovtsev; Falco Girgis

Macros

Detailed Description