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Independent SDK for the Sega Dreamcast
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pvr_regs.h
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1/* KallistiOS ##version##
2
3 dc/pvr/pvr_regs.h
4 Copyright (C) 2002 Megan Potter
5 Copyright (C) 2014 Lawrence Sebald
6 Copyright (C) 2023, 2025 Ruslan Rostovtsev
7 Copyright (C) 2024 Falco Girgis
8*/
9
10/** \file dc/pvr/pvr_regs.h
11 \brief PVR Driver Registers
12 \ingroup pvr_registers
13
14 This file provides the low-level driver implementation details for the
15 PowerVR API, including its memory map and register accessors.
16
17 \author Megan Potter
18 \author Roger Cattermole
19 \author Paul Boese
20 \author Brian Paul
21 \author Lawrence Sebald
22 \author Benoit Miller
23 \author Ruslan Rostovtsev
24 \author Falco Girgis
25*/
26
27#ifndef __DC_PVR_PVR_REGS_H
28#define __DC_PVR_PVR_REGS_H
29
30#include <kos/cdefs.h>
31__BEGIN_DECLS
32
33#include <arch/arch.h>
34
35/**** Register macros ***************************************************/
36
37/** \defgroup pvr_registers Registers
38 \brief Direct PVR register and memory access
39 \ingroup pvr
40 @{
41*/
42
43/* We use these macros to do all PVR register access, so that it's
44 simple later on to hook them for debugging or whatnot. */
45
46/** \brief Retrieve a PVR register value
47
48 \param REG The register to fetch. See \ref pvr_regs.
49
50 \return The value of that register (32-bits)
51*/
52#define PVR_GET(REG) (* ( (vuint32*)( 0xa05f8000 + (REG) ) ) )
53
54/** \brief Set a PVR register value
55
56 \param REG The register to set. See \ref pvr_regs.
57 \param VALUE The value to set in the register (32-bits)
58*/
59#define PVR_SET(REG, VALUE) PVR_GET(REG) = (VALUE)
60
61/** @} */
62
63/** \defgroup pvr_regs Offsets
64 \brief PowerVR register offsets
65 \ingroup pvr_registers
66
67 The registers themselves; these are from Maiwe's powervr-reg.txt.
68
69 \note
70 2D specific registers have been excluded for now (like
71 vsync, hsync, v/h size, etc)
72
73 @{
74*/
75
76#define PVR_ID 0x0000 /**< \brief Chip ID */
77#define PVR_REVISION 0x0004 /**< \brief Chip revision */
78#define PVR_RESET 0x0008 /**< \brief Reset pins */
79
80#define PVR_ISP_START 0x0014 /**< \brief Start the ISP/TSP */
81#define PVR_UNK_0018 0x0018 /**< \brief ?? */
82
83#define PVR_ISP_VERTBUF_ADDR 0x0020 /**< \brief Vertex buffer address for scene rendering */
84
85#define PVR_ISP_TILEMAT_ADDR 0x002c /**< \brief Tile matrix address for scene rendering */
86#define PVR_SPANSORT_CFG 0x0030 /**< \brief ?? -- write 0x101 for now */
87
88#define PVR_BORDER_COLOR 0x0040 /**< \brief Border Color in RGB888 */
89#define PVR_FB_CFG_1 0x0044 /**< \brief Framebuffer config 1 */
90#define PVR_FB_CFG_2 0x0048 /**< \brief Framebuffer config 2 */
91#define PVR_RENDER_MODULO 0x004c /**< \brief Render modulo */
92#define PVR_FB_ADDR 0x0050 /**< \brief Framebuffer start address */
93#define PVR_FB_IL_ADDR 0x0054 /**< \brief Framebuffer odd-field start address for interlace */
94
95#define PVR_FB_SIZE 0x005c /**< \brief Framebuffer display size */
96#define PVR_RENDER_ADDR 0x0060 /**< \brief Render output address */
97#define PVR_RENDER_ADDR_2 0x0064 /**< \brief Output for strip-buffering */
98#define PVR_PCLIP_X 0x0068 /**< \brief Horizontal clipping area */
99#define PVR_PCLIP_Y 0x006c /**< \brief Vertical clipping area */
100
101#define PVR_CHEAP_SHADOW 0x0074 /**< \brief Cheap shadow control */
102#define PVR_OBJECT_CLIP 0x0078 /**< \brief Distance for polygon culling */
103#define PVR_UNK_007C 0x007c /**< \brief ?? -- write 0x0027df77 for now */
104#define PVR_UNK_0080 0x0080 /**< \brief ?? -- write 7 for now */
105#define PVR_TEXTURE_CLIP 0x0084 /**< \brief Distance for texture clipping */
106#define PVR_BGPLANE_Z 0x0088 /**< \brief Distance for background plane */
107#define PVR_BGPLANE_CFG 0x008c /**< \brief Background plane config */
108
109#define PVR_UNK_0098 0x0098 /**< \brief ?? -- write 0x00800408 for now */
110
111#define PVR_UNK_00A0 0x00a0 /**< \brief ?? -- write 0x20 for now */
112
113#define PVR_UNK_00A8 0x00a8 /**< \brief ?? -- write 0x15d1c951 for now */
114
115#define PVR_FOG_TABLE_COLOR 0x00b0 /**< \brief Table fog color */
116#define PVR_FOG_VERTEX_COLOR 0x00b4 /**< \brief Vertex fog color */
117#define PVR_FOG_DENSITY 0x00b8 /**< \brief Fog density coefficient */
118#define PVR_COLOR_CLAMP_MAX 0x00bc /**< \brief RGB Color clamp max */
119#define PVR_COLOR_CLAMP_MIN 0x00c0 /**< \brief RGB Color clamp min */
120#define PVR_GUN_POS 0x00c4 /**< \brief Light gun position */
121#define PVR_HPOS_IRQ 0x00c8 /**< \brief Horizontal position IRQ */
122#define PVR_VPOS_IRQ 0x00cc /**< \brief Vertical position IRQ */
123#define PVR_IL_CFG 0x00d0 /**< \brief Interlacing config */
124#define PVR_BORDER_X 0x00d4 /**< \brief Window border X position */
125#define PVR_SCAN_CLK 0x00d8 /**< \brief Clock and scanline values */
126#define PVR_BORDER_Y 0x00dc /**< \brief Window border Y position */
127
128#define PVR_TEXTURE_MODULO 0x00e4 /**< \brief Output texture width modulo */
129#define PVR_VIDEO_CFG 0x00e8 /**< \brief Misc video config */
130#define PVR_BITMAP_X 0x00ec /**< \brief Bitmap window X position */
131#define PVR_BITMAP_Y 0x00f0 /**< \brief Bitmap window Y position */
132#define PVR_SCALER_CFG 0x00f4 /**< \brief Smoothing scaler */
133
134#define PVR_PALETTE_CFG 0x0108 /**< \brief Palette format */
135#define PVR_SYNC_STATUS 0x010c /**< \brief V/H blank status */
136#define PVR_UNK_0110 0x0110 /**< \brief ?? -- write 0x93f39 for now */
137#define PVR_UNK_0114 0x0114 /**< \brief ?? -- write 0x200000 for now */
138#define PVR_UNK_0118 0x0118 /**< \brief ?? -- write 0x8040 for now */
139
140#define PVR_TA_OPB_START 0x0124 /**< \brief Object Pointer Buffer start for TA usage */
141#define PVR_TA_VERTBUF_START 0x0128 /**< \brief Vertex buffer start for TA usage */
142#define PVR_TA_OPB_END 0x012c /**< \brief OPB end for TA usage */
143#define PVR_TA_VERTBUF_END 0x0130 /**< \brief Vertex buffer end for TA usage */
144#define PVR_TA_OPB_POS 0x0134 /**< \brief Top used memory location in OPB for TA usage */
145#define PVR_TA_VERTBUF_POS 0x0138 /**< \brief Top used memory location in vertbuf for TA usage */
146#define PVR_TILEMAT_CFG 0x013c /**< \brief Tile matrix size config */
147#define PVR_OPB_CFG 0x0140 /**< \brief Active lists / list size */
148#define PVR_TA_INIT 0x0144 /**< \brief Initialize vertex reg. params */
149#define PVR_YUV_ADDR 0x0148 /**< \brief YUV conversion destination */
150#define PVR_YUV_CFG 0x014c /**< \brief YUV configuration */
151#define PVR_YUV_STAT 0x0150 /**< \brief The number of YUV macroblocks converted */
152
153#define PVR_UNK_0160 0x0160 /**< \brief ?? */
154#define PVR_TA_OPB_INIT 0x0164 /**< \brief Object pointer buffer position init */
155
156#define PVR_FOG_TABLE_BASE 0x0200 /**< \brief Base of the fog table */
157
158#define PVR_PALETTE_TABLE_BASE 0x1000 /**< \brief Base of the palette table */
159/** @} */
160
161/** \defgroup pvr_addresses Addresses and Constants
162 \brief Miscellaneous Addresses and Constants
163 \ingroup pvr_registers
164
165 Useful PVR memory locations and values.
166
167 @{
168*/
169#define PVR_TA_INPUT 0x10000000 /**< \brief TA command input (64-bit, TA) */
170#define PVR_TA_YUV_CONV 0x10800000 /**< \brief YUV converter (64-bit, TA) */
171#define PVR_TA_TEX_MEM 0x11000000 /**< \brief VRAM 64-bit, TA=>VRAM */
172#define PVR_TA_TEX_MEM_32 0x13000000 /**< \brief VRAM 32-bit, TA->VRAM */
173#define PVR_RAM_BASE_32_P0 0x05000000 /**< \brief VRAM 32-bit, P0 area, PVR->VRAM */
174#define PVR_RAM_BASE_64_P0 0x04000000 /**< \brief VRAM 64-bit, P0 area, PVR->VRAM */
175#define PVR_RAM_BASE 0xa5000000 /**< \brief VRAM 32-bit, P2 area, PVR->VRAM */
176#define PVR_RAM_INT_BASE 0xa4000000 /**< \brief VRAM 64-bit, P2 area, PVR->VRAM */
177
178#define PVR_RAM_SIZE_MB (hardware_sys_mode(NULL) == HW_TYPE_RETAIL ? 8 : 16) /**< \brief RAM size in MiB */
179#define PVR_RAM_SIZE (PVR_RAM_SIZE_MB*1024*1024) /**< \brief RAM size in bytes */
180
181#define PVR_RAM_TOP (PVR_RAM_BASE + PVR_RAM_SIZE) /**< \brief Top of raw PVR RAM */
182#define PVR_RAM_INT_TOP (PVR_RAM_INT_BASE + PVR_RAM_SIZE) /**< \brief Top of int PVR RAM */
183/** @} */
184
185/* Register content defines, as needed; these will be filled in over time
186 as the implementation requires them. There's too many to do otherwise. */
187
188/** \defgroup pvr_reset_vals Reset Values
189 \brief Values used to reset parts of the PVR
190 \ingroup pvr_registers
191
192 These values are written to the PVR_RESET register in order to reset the
193 system or to take it out of reset.
194
195 @{
196*/
197#define PVR_RESET_ALL 0xffffffff /**< \brief Reset the whole PVR */
198#define PVR_RESET_NONE 0x00000000 /**< \brief Cancel reset state */
199#define PVR_RESET_TA 0x00000001 /**< \brief Reset only the TA */
200#define PVR_RESET_ISPTSP 0x00000002 /**< \brief Reset only the ISP/TSP */
201/** @} */
202
203/** \defgroup pvr_go Init/Start Values
204 \brief Values to be written to registers to conform or start operations.
205 \ingroup pvr_registers
206 @{
207*/
208#define PVR_ISP_START_GO 0xffffffff /**< \brief Write to the PVR_ISP_START register to start rendering */
209
210#define PVR_TA_INIT_GO 0x80000000 /**< \brief Write to the PVR_TA_INIT register to confirm settings */
211/** @} */
212
213/** \defgroup pvr_tex_mod PVR_TEXTURE_MODULO Values
214 \brief Definitions for the contents of the PVR_TEXTURE_MODULO register.
215 \ingroup pvr_registers
216 @{
217*/
218#define PVR_TXR_STRIDE_MULT GENMASK(4, 0) /**< \brief Bottom 5 bits contain the size when using PVR_TXRFMT_X32_STRIDE */
219/** @} */
220
221/** \defgroup pvr_scaler PVR_SCALER_CFG Values
222 \brief Definitions for the fields of the PVR_SCALER_CFG register.
223 \ingroup pvr_registers
224 @{
225*/
226#define PVR_SCALER_CFG_FSAA BIT(16) /**< \brief Enable FSAA */
227
228#define PVR_SCALER_CFG_VSCALE_FACTOR GENMASK(15, 0) /**< \brief Vertical scale factor = 1024 / value */
229/** @} */
230
231__END_DECLS
232
233#endif /* __DC_PVR_PVR_REGS_H */
arch.h
Dreamcast architecture specific options.
cdefs.h
Various common macros used throughout the codebase.