KallistiOS git master
Independent SDK for the Sega Dreamcast
Loading...
Searching...
No Matches
pvr_regs.h
Go to the documentation of this file.
1/* KallistiOS ##version##
2
3 dc/pvr/pvr_regs.h
4 Copyright (C) 2002 Megan Potter
5 Copyright (C) 2014 Lawrence Sebald
6 Copyright (C) 2023, 2025, 2026 Ruslan Rostovtsev
7 Copyright (C) 2024 Falco Girgis
8*/
9
10/** \file dc/pvr/pvr_regs.h
11 \brief PVR Driver Registers
12 \ingroup pvr_registers
13
14 This file provides the low-level driver implementation details for the
15 PowerVR API, including its memory map and register accessors.
16
17 \author Megan Potter
18 \author Roger Cattermole
19 \author Paul Boese
20 \author Brian Paul
21 \author Lawrence Sebald
22 \author Benoit Miller
23 \author Ruslan Rostovtsev
24 \author Falco Girgis
25*/
26
27#ifndef __DC_PVR_PVR_REGS_H
28#define __DC_PVR_PVR_REGS_H
29
30#include <kos/cdefs.h>
31__BEGIN_DECLS
32
33#include <arch/arch.h>
34
35/**** Register macros ***************************************************/
36
37/** \defgroup pvr_registers Registers
38 \brief Direct PVR register and memory access
39 \ingroup pvr
40 @{
41*/
42
43/* We use these macros to do all PVR register access, so that it's
44 simple later on to hook them for debugging or whatnot. */
45
46/** \brief Retrieve a PVR register value
47
48 \param REG The register to fetch. See \ref pvr_regs.
49
50 \return The value of that register (32-bits)
51*/
52#define PVR_GET(REG) (* ( (volatile uint32_t *)( 0xa05f8000 + (REG) ) ) )
53
54/** \brief Set a PVR register value
55
56 \param REG The register to set. See \ref pvr_regs.
57 \param VALUE The value to set in the register (32-bits)
58*/
59#define PVR_SET(REG, VALUE) PVR_GET(REG) = (VALUE)
60
61/** \brief Address stride from CLXA to CLXB (registers and VRAM windows).
62
63 NAOMI 2 only. The second PVR is not mapped until \ref pvr2_init().
64*/
65#define PVR2_ADDR_STRIDE 0x02000000
66
67/** \brief Retrieve a register from the second PVR (CLXB). */
68#define PVR2_GET(REG) (* ( (volatile uint32_t *)( 0xa25f8000 + (REG) ) ) )
69
70/** \brief Set a register on the second PVR (CLXB). */
71#define PVR2_SET(REG, VALUE) PVR2_GET(REG) = (VALUE)
72
73/** \brief Write a PVR register to both chips (write-only broadcast). */
74#define PVR_BCAST_SET(REG, VALUE) \
75 (* ( (volatile uint32_t *)( 0xa85f8000 + (REG) ) ) = (VALUE))
76
77/** @} */
78
79/** \defgroup pvr_regs Offsets
80 \brief PowerVR register offsets
81 \ingroup pvr_registers
82
83 The registers themselves; these are from Maiwe's powervr-reg.txt.
84
85 \note
86 2D specific registers have been excluded for now (like
87 vsync, hsync, v/h size, etc)
88
89 @{
90*/
91
92#define PVR_ID 0x0000 /**< \brief Chip ID */
93#define PVR_REVISION 0x0004 /**< \brief Chip revision */
94#define PVR_RESET 0x0008 /**< \brief Reset pins */
95
96#define PVR_ISP_START 0x0014 /**< \brief Start the ISP/TSP */
97#define PVR_TEST_SELECT 0x0018 /**< \brief Test select (writes prohibited) */
98
99#define PVR_ISP_VERTBUF_ADDR 0x0020 /**< \brief Vertex buffer address for scene rendering */
100
101#define PVR_ISP_TILEMAT_ADDR 0x002c /**< \brief Tile matrix address for scene rendering */
102#define PVR_SPANSORT_CFG 0x0030 /**< \brief Span sorter control -- write 0x101 for now */
103
104#define PVR_BORDER_COLOR 0x0040 /**< \brief Border Color in RGB888 */
105#define PVR_FB_CFG_1 0x0044 /**< \brief Framebuffer config 1 */
106#define PVR_FB_CFG_2 0x0048 /**< \brief Framebuffer config 2 */
107#define PVR_RENDER_MODULO 0x004c /**< \brief Render modulo */
108#define PVR_FB_ADDR 0x0050 /**< \brief Framebuffer start address */
109#define PVR_FB_IL_ADDR 0x0054 /**< \brief Framebuffer odd-field start address for interlace */
110
111#define PVR_FB_SIZE 0x005c /**< \brief Framebuffer display size */
112#define PVR_RENDER_ADDR 0x0060 /**< \brief Render output address */
113#define PVR_RENDER_ADDR_2 0x0064 /**< \brief Output for strip-buffering */
114#define PVR_PCLIP_X 0x0068 /**< \brief Horizontal clipping area */
115#define PVR_PCLIP_Y 0x006c /**< \brief Vertical clipping area */
116
117#define PVR_CHEAP_SHADOW 0x0074 /**< \brief Cheap shadow control */
118#define PVR_OBJECT_CLIP 0x0078 /**< \brief Distance for polygon culling */
119#define PVR_FPU_PARAM_CFG 0x007c /**< \brief Parameter read control -- write 0x0027df77 for now */
120#define PVR_HALF_OFFSET 0x0080 /**< \brief Pixel sampling control -- write 7 for now */
121#define PVR_TEXTURE_CLIP 0x0084 /**< \brief Distance for texture clipping */
122#define PVR_BGPLANE_Z 0x0088 /**< \brief Distance for background plane */
123#define PVR_BGPLANE_CFG 0x008c /**< \brief Background plane config */
124
125#define PVR_ISP_FEED_CFG 0x0098 /**< \brief Translucent polygon sort mode -- write 0x00800408 for now */
126
127#define PVR_SDRAM_REFRESH 0x00a0 /**< \brief Texture memory refresh counter -- write 0x20 for now */
128#define PVR_SDRAM_ARB_CFG 0x00a4 /**< \brief Texture memory arbiter control -- write 0x1f on NAOMI */
129
130#define PVR_SDRAM_CFG 0x00a8 /**< \brief Texture memory control -- write 0x15d1c951 (DC) / 0x15d1c955 (NAOMI) */
131
132#define PVR_FOG_TABLE_COLOR 0x00b0 /**< \brief Table fog color */
133#define PVR_FOG_VERTEX_COLOR 0x00b4 /**< \brief Vertex fog color */
134#define PVR_FOG_DENSITY 0x00b8 /**< \brief Fog density coefficient */
135#define PVR_COLOR_CLAMP_MAX 0x00bc /**< \brief RGB Color clamp max */
136#define PVR_COLOR_CLAMP_MIN 0x00c0 /**< \brief RGB Color clamp min */
137#define PVR_GUN_POS 0x00c4 /**< \brief Light gun position */
138#define PVR_HPOS_IRQ 0x00c8 /**< \brief Horizontal position IRQ */
139#define PVR_VPOS_IRQ 0x00cc /**< \brief Vertical position IRQ */
140#define PVR_IL_CFG 0x00d0 /**< \brief Interlacing config */
141#define PVR_BORDER_X 0x00d4 /**< \brief Window border X position */
142#define PVR_SCAN_CLK 0x00d8 /**< \brief Clock and scanline values */
143#define PVR_BORDER_Y 0x00dc /**< \brief Window border Y position */
144
145#define PVR_TEXTURE_MODULO 0x00e4 /**< \brief Output texture width modulo */
146#define PVR_VIDEO_CFG 0x00e8 /**< \brief Misc video config */
147#define PVR_BITMAP_X 0x00ec /**< \brief Bitmap window X position */
148#define PVR_BITMAP_Y 0x00f0 /**< \brief Bitmap window Y position */
149#define PVR_SCALER_CFG 0x00f4 /**< \brief Smoothing scaler */
150
151#define PVR_PALETTE_CFG 0x0108 /**< \brief Palette format */
152#define PVR_SYNC_STATUS 0x010c /**< \brief V/H blank status */
153#define PVR_FB_BURSTCTRL 0x0110 /**< \brief Framebuffer burst control -- write 0x93f39 for now */
154#define PVR_FB_C_SOF 0x0114 /**< \brief Current framebuffer start address (read) */
155#define PVR_Y_COEFF 0x0118 /**< \brief Y scaling coefficient -- write 0x8040 for now */
156
157#define PVR_PT_ALPHA_REF 0x011c /**< \brief Only pixels with alpha >= this value are drawn for Punch Through polygons */
158
159#define PVR_TA_OPB_START 0x0124 /**< \brief Object Pointer Buffer start for TA usage */
160#define PVR_TA_VERTBUF_START 0x0128 /**< \brief Vertex buffer start for TA usage */
161#define PVR_TA_OPB_END 0x012c /**< \brief OPB end for TA usage */
162#define PVR_TA_VERTBUF_END 0x0130 /**< \brief Vertex buffer end for TA usage */
163#define PVR_TA_OPB_POS 0x0134 /**< \brief Top used memory location in OPB for TA usage */
164#define PVR_TA_VERTBUF_POS 0x0138 /**< \brief Top used memory location in vertbuf for TA usage */
165#define PVR_TILEMAT_CFG 0x013c /**< \brief Tile matrix size config */
166#define PVR_OPB_CFG 0x0140 /**< \brief Active lists / list size */
167#define PVR_TA_INIT 0x0144 /**< \brief Initialize vertex reg. params */
168#define PVR_YUV_ADDR 0x0148 /**< \brief YUV conversion destination */
169#define PVR_YUV_CFG 0x014c /**< \brief YUV configuration */
170#define PVR_YUV_STAT 0x0150 /**< \brief The number of YUV macroblocks converted */
171
172#define PVR_TA_LIST_CONT 0x0160 /**< \brief TA list continuation */
173#define PVR_TA_OPB_INIT 0x0164 /**< \brief Object pointer buffer position init */
174
175#define PVR_FOG_TABLE_BASE 0x0200 /**< \brief Base of the fog table */
176
177#define PVR_PALETTE_TABLE_BASE 0x1000 /**< \brief Base of the palette table */
178/** @} */
179
180/** \defgroup pvr_addresses Addresses and Constants
181 \brief Miscellaneous Addresses and Constants
182 \ingroup pvr_registers
183
184 Useful PVR memory locations and values.
185
186 @{
187*/
188#define PVR_TA_INPUT 0x10000000 /**< \brief TA command input (64-bit, TA) */
189#define PVR_TA_YUV_CONV 0x10800000 /**< \brief YUV converter (64-bit, TA) */
190#define PVR_TA_TEX_MEM 0x11000000 /**< \brief VRAM 64-bit, TA=>VRAM */
191#define PVR_TA_TEX_MEM_32 0x13000000 /**< \brief VRAM 32-bit, TA->VRAM */
192#define PVR_RAM_BASE_32_P0 0x05000000 /**< \brief VRAM 32-bit, P0 area, PVR->VRAM */
193#define PVR_RAM_BASE_64_P0 0x04000000 /**< \brief VRAM 64-bit, P0 area, PVR->VRAM */
194#define PVR_RAM_BASE 0xa5000000 /**< \brief VRAM 32-bit, P2 area, PVR->VRAM */
195#define PVR_RAM_INT_BASE 0xa4000000 /**< \brief VRAM 64-bit, P2 area, PVR->VRAM */
196
197#define PVR_RAM_SIZE_MB (hardware_sys_mode(NULL) == HW_TYPE_RETAIL ? 8 : 16) /**< \brief RAM size in MiB */
198#define PVR_RAM_SIZE (PVR_RAM_SIZE_MB*1024*1024) /**< \brief RAM size in bytes */
199
200#define PVR_RAM_TOP (PVR_RAM_BASE + PVR_RAM_SIZE) /**< \brief Top of raw PVR RAM */
201#define PVR_RAM_INT_TOP (PVR_RAM_INT_BASE + PVR_RAM_SIZE) /**< \brief Top of int PVR RAM */
202
203#define PVR2_RAM_BASE_32_P0 (PVR_RAM_BASE_32_P0 + PVR2_ADDR_STRIDE) /**< \brief CLXB VRAM 32-bit, P0 */
204#define PVR2_RAM_BASE_64_P0 (PVR_RAM_BASE_64_P0 + PVR2_ADDR_STRIDE) /**< \brief CLXB VRAM 64-bit, P0 */
205#define PVR2_RAM_BASE (PVR_RAM_BASE + PVR2_ADDR_STRIDE) /**< \brief CLXB VRAM 32-bit, P2 */
206#define PVR2_RAM_INT_BASE (PVR_RAM_INT_BASE + PVR2_ADDR_STRIDE) /**< \brief CLXB VRAM 64-bit, P2 */
207#define PVR2_RAM_TOP (PVR2_RAM_BASE + PVR_RAM_SIZE) /**< \brief Top of CLXB 32-bit VRAM */
208#define PVR2_RAM_INT_TOP (PVR2_RAM_INT_BASE + PVR_RAM_SIZE) /**< \brief Top of CLXB 64-bit VRAM */
209/** @} */
210
211/* Register content defines, as needed; these will be filled in over time
212 as the implementation requires them. There's too many to do otherwise. */
213
214/** \defgroup pvr_reset_vals Reset Values
215 \brief Values used to reset parts of the PVR
216 \ingroup pvr_registers
217
218 These values are written to the PVR_RESET register in order to reset the
219 system or to take it out of reset.
220
221 @{
222*/
223#define PVR_RESET_ALL 0xffffffff /**< \brief Reset the whole PVR */
224#define PVR_RESET_NONE 0x00000000 /**< \brief Cancel reset state */
225#define PVR_RESET_TA 0x00000001 /**< \brief Reset only the TA */
226#define PVR_RESET_ISPTSP 0x00000002 /**< \brief Reset only the ISP/TSP */
227/** @} */
228
229/** \defgroup pvr_go Init/Start Values
230 \brief Values to be written to registers to conform or start operations.
231 \ingroup pvr_registers
232 @{
233*/
234#define PVR_ISP_START_GO 0xffffffff /**< \brief Write to the PVR_ISP_START register to start rendering */
235
236#define PVR_TA_INIT_GO 0x80000000 /**< \brief Write to the PVR_TA_INIT register to confirm settings */
237/** @} */
238
239/** \defgroup pvr_tex_mod PVR_TEXTURE_MODULO Values
240 \brief Definitions for the contents of the PVR_TEXTURE_MODULO register.
241 \ingroup pvr_registers
242 @{
243*/
244#define PVR_TXR_STRIDE_MULT GENMASK(4, 0) /**< \brief Bottom 5 bits contain the size when using PVR_TXRFMT_X32_STRIDE */
245/** @} */
246
247/** \defgroup pvr_scaler PVR_SCALER_CFG Values
248 \brief Definitions for the fields of the PVR_SCALER_CFG register.
249 \ingroup pvr_registers
250 @{
251*/
252#define PVR_SCALER_CFG_FSAA BIT(16) /**< \brief Enable FSAA */
253
254#define PVR_SCALER_CFG_VSCALE_FACTOR GENMASK(15, 0) /**< \brief Vertical scale factor = 1024 / value */
255/** @} */
256
257__END_DECLS
258
259#endif /* __DC_PVR_PVR_REGS_H */
arch.h
Dreamcast architecture specific options.
cdefs.h
Various common macros used throughout the codebase.