mmu.h File Reference

Memory Management Unit and Translation Lookaside Buffer handling. More...

#include <sys/cdefs.h>
#include <stdbool.h>
#include <arch/types.h>
#include <sys/uio.h>

Go to the source code of this file.

Data Structures
struct	mmupage_t
	MMU TLB entry for a single page. More...
struct	mmusubcontext_t
	MMU sub-context type. More...
struct	mmucontext_t
	MMU context type. More...

Macros
#define	MMU_SUB_PAGES   512
	The number of pages in a sub-context.
#define	MMU_PAGES   1024
	The number of sub-contexts in the main level context.

Typedefs
typedef mmupage_t *(*	mmu_mapfunc_t) (mmucontext_t *context, int virtpage)
	MMU mapping handler.

Enumerations
enum	page_prot_t { MMU_KERNEL_RDONLY , MMU_KERNEL_RDWR , MMU_ALL_RDONLY , MMU_ALL_RDWR }
enum	page_cache_t { MMU_NO_CACHE , MMU_CACHE_BACK , MMU_CACHE_WT , MMU_CACHEABLE = MMU_CACHE_BACK }
enum	page_size_t { PAGE_SIZE_1K , PAGE_SIZE_4K , PAGE_SIZE_64K , PAGE_SIZE_1M }

Functions
void	mmu_use_table (mmucontext_t *context)
	Set the "current" page tables for TLB handling.
mmucontext_t *	mmu_context_create (int asid)
	Allocate a new MMU context.
void	mmu_context_destroy (mmucontext_t *context)
	Destroy an MMU context when a process is being destroyed.
int	mmu_virt_to_phys (mmucontext_t *context, int virtpage)
	Using the given page tables, translate the virtual page ID to a physical page ID.
int	mmu_phys_to_virt (mmucontext_t *context, int physpage)
	Using the given page tables, translate the physical page ID to a virtual page ID.
void	mmu_switch_context (mmucontext_t *context)
	Switch to the given context.
void	mmu_page_map (mmucontext_t *context, int virtpage, int physpage, int count, page_prot_t prot, page_cache_t cache, bool share, bool dirty)
	Set the given virtual page to map to the given physical page.
int	mmu_copyin (mmucontext_t *context, uint32_t srcaddr, uint32_t srccnt, void *buffer)
	Copy a chunk of data from a process' address space into a kernel buffer, taking into account page mappings.
int	mmu_copyv (mmucontext_t *context1, struct iovec *iov1, int iovcnt1, mmucontext_t *context2, struct iovec *iov2, int iovcnt2)
	Copy a chunk of data from one process' address space to another process' address space, taking into account page mappings.
mmu_mapfunc_t	mmu_map_get_callback (void)
	Get the current mapping function.
mmu_mapfunc_t	mmu_map_set_callback (mmu_mapfunc_t newfunc)
	Set a new MMU mapping handler.
int	mmu_page_map_static (uintptr_t virt, uintptr_t phys, page_size_t page_size, page_prot_t page_prot, bool cached)
	Create a static virtual memory maping.
void	mmu_init (void)
	Initialize MMU support.
void	mmu_init_basic (void)
	Initialize basic MMU support.
void	mmu_shutdown (void)
	Shutdown MMU support.
void	mmu_shutdown_basic (void)
	Shutdown basic MMU support.
void	mmu_reset_itlb (void)
	Reset ITLB.
bool	mmu_enabled (void)
	Check if MMU translation is enabled.
void	mmu_set_sq_addr (void *addr)
	Reset the base target address for store queues.

Detailed Description

Memory Management Unit and Translation Lookaside Buffer handling.

This file defines the interface to the Memory Management Unit (MMU) in the SH4. The MMU, while not used normally by KOS, is available for virtual memory use, if you so desire. While using this functionality is probably overkill for most homebrew, there are a few very interesting things that this functionality could be used for (like mapping large files into memory that wouldn't otherwise fit).

The whole system is set up as a normal paged memory virtual->physical address translation. KOS implements the page table as a sparse, two-level page table. By default, pages are 4KB in size. Each top-level page table entry has 512 2nd level entries (there are 1024 entries in the top-level entry). This works out to about 2KB of space needed for one top-level entry.

The SH4 itself has 4 TLB entries for instruction fetches, and 64 "unified" TLB entries (for combined instructions + data). Essentially, the UTLB acts both as the TLB for data accesses (from mov instructions) and as a cache for entries for the ITLB. If there is no entry in the ITLB for an instruction access, the UTLB will automatically be searched. If no entry is found still, an ITLB miss exception will be generated. Data accesses are handled similarly to this (although additional complications are involved due to write accesses, and of course the ITLB doesn't play into data accesses).

For more information about how the MMU works, refer to the Hitachi/Renesas SH4 programming manual. It has much more detailed information than what is in here, for obvious reasons.

This functionality was ported over to mainline KOS from the KOS-MMU project of Megan Potter. Unfortunately, KOS-MMU never reached a real phase of maturity and usefulness, but this piece can be quite useful on its own.

Author

Megan Potter

Macro Definition Documentation

MMU_PAGES

#define MMU_PAGES   1024

The number of sub-contexts in the main level context.