MMU TLB entry for a single page. More...

#include <arch/mmu.h>

Data Fields
uint32	physical: 18
	Physical page ID – 18 bits.

uint32	prkey: 2
	Protection key data – 2 bits.

uint32	valid: 1
	Valid mapping – 1 bit.

uint32	shared: 1
	Shared between procs – 1 bit.

uint32	cache: 1
	Cacheable – 1 bit.

uint32	dirty: 1
	Dirty – 1 bit.

uint32	wthru: 1
	Write-thru enable – 1 bit.

uint32	blank: 7
	Reserved – 7 bits.

uint32	pteh
	Pre-built PTEH value.

uint32	ptel
	Pre-built PTEL value.

Detailed Description

MMU TLB entry for a single page.

The TLB entries on the SH4 are a single 32-bit dword in length. We store some other data here too for ease of use.

Field Documentation

◆ blank

uint32 mmupage_t::blank

Reserved – 7 bits.

◆ cache

uint32 mmupage_t::cache

Cacheable – 1 bit.

◆ dirty

uint32 mmupage_t::dirty

Dirty – 1 bit.

◆ physical

uint32 mmupage_t::physical

Physical page ID – 18 bits.

◆ prkey

uint32 mmupage_t::prkey

Protection key data – 2 bits.

◆ pteh

uint32 mmupage_t::pteh

Pre-built PTEH value.

◆ ptel

uint32 mmupage_t::ptel

Pre-built PTEL value.

◆ shared

uint32 mmupage_t::shared

Shared between procs – 1 bit.

◆ valid

uint32 mmupage_t::valid

Valid mapping – 1 bit.

◆ wthru

uint32 mmupage_t::wthru

Write-thru enable – 1 bit.

The documentation for this struct was generated from the following file:

kernel/arch/dreamcast/include/arch/mmu.h

Data Fields