elan.h File Reference

VideoLogic Elan T&L coprocessor (NAOMI 2). More...

#include <kos/cdefs.h>
#include <stdbool.h>
#include <stdint.h>
#include <kos/regfield.h>
#include <dc/memory.h>

Go to the source code of this file.

Macros
#define	ELAN_BASE   0xa8800000
	Elan register block, P2.
#define	ELAN_MAGIC   0xe1ad0000
	Value of ELAN_REG_ID on a present Elan.
#define	ELAN_RAM_BASE_P0   0x0a000000
	Elan local RAM, P0.
#define	ELAN_RAM_BASE   (MEM_AREA_P2_BASE | ELAN_RAM_BASE_P0)
	Elan local RAM, P2.
#define	ELAN_RAM_SIZE   (32 * 1024 * 1024)
	Elan local RAM size in bytes.
#define	ELAN_REG_ID   0x00
	Magic (ELAN_MAGIC)
#define	ELAN_REG_REVISION   0x04
	Chip revision.
#define	ELAN_REG_CMDQ   0x0c
	Command queue occupancy.
#define	ELAN_REG_IFCTL   0x10
	SH-4 / PVR interface.
#define	ELAN_REG_REFRESH   0x14
	SDRAM refresh.
#define	ELAN_REG_SDRAMCFG   0x1c
	SDRAM config.
#define	ELAN_REG_TILER   0x30
	Macro tiler.
#define	ELAN_REG_IRQSTAT   0x74
	IRQ status.
#define	ELAN_REG_IRQMASK   0x78
	IRQ mask.
#define	ELAN_IFCTL_CS1_BCAST   BIT(0)
	Broadcast writes on CS1 (both PVRs)
#define	ELAN_IFCTL_CH2   BIT(1)
	Elan channel 2.
#define	ELAN_IFCTL_PVR2   BIT(2)
	Enable CLXB address windows.
#define	ELAN_GET(reg)
	Read an Elan register.
#define	ELAN_SET(reg, value)
	Write an Elan register.

Functions
bool	elan_present (void)
	True when Elan is present (NAOMI 2).
uint32_t	elan_revision (void)
	Elan revision register, or 0 if absent.
uint32_t	elan_ifctl_get (void)
	Current IFCTL value, or 0 if Elan is absent.
void	elan_ifctl_set (uint32_t value)
	Write IFCTL.
void	elan_pvr2_enable (void)
	Enable CLXB address windows (IFCTL bit 2, never bit 0).
void	elan_pvr2_disable (void)
	Disable CLXB address windows (IFCTL = 0).
bool	elan_pvr2_enabled (void)
	True if IFCTL bit 2 is set.

Detailed Description

VideoLogic Elan T&L coprocessor (NAOMI 2).

Elan is the geometry processor on NAOMI 2 and has 32 MB of local RAM. IFCTL bit 2 enables CLXB's register and VRAM windows; they are left disabled at boot.

Call pvr2_init() when CPU access to CLXB VRAM is required. Do not set ELAN_IFCTL_CS1_BCAST unless you intend to broadcast CS1 writes to both GPUs.

Author

Ruslan Rostovtsev