VideoLogic Elan T&L coprocessor (NAOMI 2)
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| file | elan.h |
| | VideoLogic Elan T&L coprocessor (NAOMI 2).
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| |
VideoLogic Elan T&L coprocessor (NAOMI 2)
◆ ELAN_BASE
| #define ELAN_BASE 0xa8800000 |
◆ ELAN_GET
Value:
#define ELAN_BASE
Elan register block, P2.
Definition elan.h:42
Read an Elan register.
◆ ELAN_MAGIC
| #define ELAN_MAGIC 0xe1ad0000 |
◆ ELAN_RAM_BASE
◆ ELAN_RAM_BASE_P0
| #define ELAN_RAM_BASE_P0 0x0a000000 |
◆ ELAN_RAM_SIZE
| #define ELAN_RAM_SIZE (32 * 1024 * 1024) |
Elan local RAM size in bytes.
◆ ELAN_SET
| #define ELAN_SET |
( |
| reg, |
|
|
| value ) |
Value:
#define ELAN_GET(reg)
Read an Elan register.
Definition elan.h:83
Write an Elan register.
◆ elan_ifctl_get()
| uint32_t elan_ifctl_get |
( |
void | | ) |
|
Current IFCTL value, or 0 if Elan is absent.
◆ elan_ifctl_set()
| void elan_ifctl_set |
( |
uint32_t | value | ) |
|
Write IFCTL.
- Warning
- Bit 0 (ELAN_IFCTL_CS1_BCAST) broadcasts CS1 to both GPUs. Leave it clear unless you are duplicating textures on purpose.
◆ elan_present()
| bool elan_present |
( |
void | | ) |
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True when Elan is present (NAOMI 2).
◆ elan_pvr2_disable()
| void elan_pvr2_disable |
( |
void | | ) |
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Disable CLXB address windows (IFCTL = 0).
◆ elan_pvr2_enable()
| void elan_pvr2_enable |
( |
void | | ) |
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Enable CLXB address windows (IFCTL bit 2, never bit 0).
◆ elan_pvr2_enabled()
| bool elan_pvr2_enabled |
( |
void | | ) |
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True if IFCTL bit 2 is set.
◆ elan_revision()
| uint32_t elan_revision |
( |
void | | ) |
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Elan revision register, or 0 if absent.