irq.h File Reference

Interrupt and exception handling. More...

#include <kos/irq.h>
#include <stdalign.h>
#include <stdbool.h>
#include <stdint.h>
#include <kos/cdefs.h>

Go to the source code of this file.

Data Structures
struct	irq_context_t
	Architecture-specific structure for holding the processor state. More...

Macros
#define	IRQ_TRAP_CODE(code)
#define	IRQ_PRIO_MAX   15
	Minimum/maximum values for IRQ priorities.
#define	IRQ_PRIO_MIN   1
#define	IRQ_PRIO_MASKED   0
#define	REG_BYTE_CNT   256
	Thread execution state and accessors.
Register Accessors
Convenience macros for accessing context registers
#define	CONTEXT_PC(c)
	Fetch the program counter from an irq_context_t.
#define	CONTEXT_FP(c)
	Fetch the frame pointer from an irq_context_t.
#define	CONTEXT_SP(c)
	Fetch the stack pointer from an irq_context_t.
#define	CONTEXT_RET(c)
	Fetch the return value from an irq_context_t.

Enumerations
enum	irq_exception {   EXC_RESET_POWERON = 0x0000 , EXC_RESET_MANUAL = 0x0020 , EXC_RESET_UDI = 0x0000 , EXC_ITLB_MULTIPLE = 0x0140 ,   EXC_DTLB_MULTIPLE = 0x0140 , EXC_USER_BREAK_PRE = 0x01e0 , EXC_INSTR_ADDRESS = 0x00e0 , EXC_ITLB_MISS = 0x0040 ,   EXC_ITLB_PV = 0x00a0 , EXC_ILLEGAL_INSTR = 0x0180 , EXC_SLOT_ILLEGAL_INSTR = 0x01a0 , EXC_GENERAL_FPU = 0x0800 ,   EXC_SLOT_FPU = 0x0820 , EXC_DATA_ADDRESS_READ = 0x00e0 , EXC_DATA_ADDRESS_WRITE = 0x0100 , EXC_DTLB_MISS_READ = 0x0040 ,   EXC_DTLB_MISS_WRITE = 0x0060 , EXC_DTLB_PV_READ = 0x00a0 , EXC_DTLB_PV_WRITE = 0x00c0 , EXC_FPU = 0x0120 ,   EXC_INITIAL_PAGE_WRITE = 0x0080 , EXC_TRAPA = 0x0160 , EXC_USER_BREAK_POST = 0x01e0 , EXC_NMI = 0x01c0 ,   EXC_IRQ0 = 0x0200 , EXC_IRQ1 = 0x0220 , EXC_IRQ2 = 0x0240 , EXC_IRQ3 = 0x0260 ,   EXC_IRQ4 = 0x0280 , EXC_IRQ5 = 0x02a0 , EXC_IRQ6 = 0x02c0 , EXC_IRQ7 = 0x02e0 ,   EXC_IRQ8 = 0x0300 , EXC_IRQ9 = 0x0320 , EXC_IRQA = 0x0340 , EXC_IRQB = 0x0360 ,   EXC_IRQC = 0x0380 , EXC_IRQD = 0x03a0 , EXC_IRQE = 0x03c0 , EXC_TMU0_TUNI0 = 0x0400 ,   EXC_TMU1_TUNI1 = 0x0420 , EXC_TMU2_TUNI2 = 0x0440 , EXC_TMU2_TICPI2 = 0x0460 , EXC_RTC_ATI = 0x0480 ,   EXC_RTC_PRI = 0x04a0 , EXC_RTC_CUI = 0x04c0 , EXC_SCI_ERI = 0x04e0 , EXC_SCI_RXI = 0x0500 ,   EXC_SCI_TXI = 0x0520 , EXC_SCI_TEI = 0x0540 , EXC_WDT_ITI = 0x0560 , EXC_REF_RCMI = 0x0580 ,   EXC_REF_ROVI = 0x05a0 , EXC_UDI = 0x0600 , EXC_GPIO_GPIOI = 0x0620 , EXC_DMAC_DMTE0 = 0x0640 ,   EXC_DMAC_DMTE1 = 0x0660 , EXC_DMAC_DMTE2 = 0x0680 , EXC_DMAC_DMTE3 = 0x06a0 , EXC_DMA_DMAE = 0x06c0 ,   EXC_SCIF_ERI = 0x0700 , EXC_SCIF_RXI = 0x0720 , EXC_SCIF_BRI = 0x0740 , EXC_SCIF_TXI = 0x0760 ,   EXC_DOUBLE_FAULT = 0x0780 , EXC_UNHANDLED_EXC = 0x07e0 , EXC_TRAP = 0x0800 }
	Interrupt exception codes. More...
enum	irq_src_t {   IRQ_SRC_RTC , IRQ_SRC_TMU2 , IRQ_SRC_TMU1 , IRQ_SRC_TMU0 ,   _IRQ_SRC_RESV , IRQ_SRC_SCI1 , IRQ_SRC_REF , IRQ_SRC_WDT ,   IRQ_SRC_HUDI , IRQ_SRC_SCIF , IRQ_SRC_DMAC , IRQ_SRC_GPIO ,   IRQ_SRC_IRL3 , IRQ_SRC_IRL2 , IRQ_SRC_IRL1 , IRQ_SRC_IRL0 }
	Interrupt sources. More...

Functions
static int	arch_irq_inside_int (void)
static void	arch_irq_restore (irq_mask_t old)
static irq_mask_t	arch_irq_disable (void)
static void	arch_irq_enable (void)
void	arch_irq_create_context (irq_context_t *context, uintptr_t stack_pointer, uintptr_t routine, const uintptr_t *args)
int	arch_irq_set_handler (irq_t code, irq_hdl_t hnd, void *data)
irq_cb_t	arch_irq_get_handler (irq_t code)
int	arch_irq_set_global_handler (irq_hdl_t hnd, void *data)
irq_cb_t	arch_irq_get_global_handler (void)
void	arch_irq_set_context (irq_context_t *cxt)
irq_context_t *	arch_irq_get_context (void)
void	irq_set_priority (irq_src_t src, unsigned int prio)
	Set the priority of a given IRQ source.
unsigned int	irq_get_priority (irq_src_t src)
	Get the priority of a given IRQ source.

Variables
int	inside_int

Detailed Description

Interrupt and exception handling.

This file contains various definitions and declarations related to handling interrupts and exceptions on the Dreamcast. This level deals with IRQs and exceptions generated on the SH4, versus the asic layer which deals with actually differentiating "external" interrupts.

Author

Megan Potter

Paul Cercueil

Falco Girgis

See also

dc/asic.h

Macro Definition Documentation

IRQ_PRIO_MASKED

#define IRQ_PRIO_MASKED   0

IRQ_PRIO_MAX

#define IRQ_PRIO_MAX   15

Minimum/maximum values for IRQ priorities.

A priority of zero means the interrupt is masked. The maximum priority that can be set is 15.

IRQ_PRIO_MIN

#define IRQ_PRIO_MIN   1

IRQ_TRAP_CODE

#define IRQ_TRAP_CODE

(

code

)

Value:

(irq_t)(EXC_TRAP + (code))

Enumeration Type Documentation

irq_exception

enum irq_exception

Interrupt exception codes.

SH-specific exception codes. Used to identify the source or type of an interrupt. Each exception code is of a certain "type" which dictates how the interrupt is generated and handled.

List of exception types:

Type	Description
RESET	Caused by system reset. Uncatchable and fatal. Automatically branch to address 0xA0000000.
REEXEC	Restarts current instruction after interrupt processing. Context PC is the triggering instruction.
POST	Continues with next instruciton after interrupt processing. Context PC is the next instruction.
SOFT	Software-driven exceptions for triggering interrupts upon special events.
UNUSED	Known to not be present and usable with the DC's SH4 configuration.
TRAP	Virtual type (not a SH hardware type) for trap codes.

List of exception codes:

Enumerator
EXC_RESET_POWERON	[RESET ] Power-on reset
EXC_RESET_MANUAL	[RESET ] Manual reset
EXC_RESET_UDI	[RESET ] Hitachi UDI reset
EXC_ITLB_MULTIPLE	[RESET ] Instruction TLB multiple hit
EXC_DTLB_MULTIPLE	[RESET ] Data TLB multiple hit
EXC_USER_BREAK_PRE	[REEXEC] User break before instruction
EXC_INSTR_ADDRESS	[REEXEC] Instruction address
EXC_ITLB_MISS	[REEXEC] Instruction TLB miss
EXC_ITLB_PV	[REEXEC] Instruction TLB protection violation
EXC_ILLEGAL_INSTR	[REEXEC] Illegal instruction
EXC_SLOT_ILLEGAL_INSTR	[REEXEC] Slot illegal instruction
EXC_GENERAL_FPU	[REEXEC] General FPU exception
EXC_SLOT_FPU	[REEXEC] Slot FPU exception
EXC_DATA_ADDRESS_READ	[REEXEC] Data address (read)
EXC_DATA_ADDRESS_WRITE	[REEXEC] Data address (write)
EXC_DTLB_MISS_READ	[REEXEC] Data TLB miss (read)
EXC_DTLB_MISS_WRITE	[REEXEC] Data TLB miss (write)
EXC_DTLB_PV_READ	[REEXEC] Data TLB protection violation (read)
EXC_DTLB_PV_WRITE	[REEXEC] Data TLB protection violation (write)
EXC_FPU	[REEXEC] FPU exception
EXC_INITIAL_PAGE_WRITE	[REEXEC] Initial page write exception
EXC_TRAPA	[POST ] Unconditional trap (TRAPA)
EXC_USER_BREAK_POST	[POST ] User break after instruction
EXC_NMI	[POST ] Nonmaskable interrupt
EXC_IRQ0	[POST ] External IRQ request (level 0)
EXC_IRQ1	[POST ] External IRQ request (level 1)
EXC_IRQ2	[POST ] External IRQ request (level 2)
EXC_IRQ3	[POST ] External IRQ request (level 3)
EXC_IRQ4	[POST ] External IRQ request (level 4)
EXC_IRQ5	[POST ] External IRQ request (level 5)
EXC_IRQ6	[POST ] External IRQ request (level 6)
EXC_IRQ7	[POST ] External IRQ request (level 7)
EXC_IRQ8	[POST ] External IRQ request (level 8)
EXC_IRQ9	[POST ] External IRQ request (level 9)
EXC_IRQA	[POST ] External IRQ request (level 10)
EXC_IRQB	[POST ] External IRQ request (level 11)
EXC_IRQC	[POST ] External IRQ request (level 12)
EXC_IRQD	[POST ] External IRQ request (level 13)
EXC_IRQE	[POST ] External IRQ request (level 14)
EXC_TMU0_TUNI0	[POST ] TMU0 underflow
EXC_TMU1_TUNI1	[POST ] TMU1 underflow
EXC_TMU2_TUNI2	[POST ] TMU2 underflow
EXC_TMU2_TICPI2	[UNUSED] TMU2 input capture
EXC_RTC_ATI	[UNUSED] RTC alarm interrupt
EXC_RTC_PRI	[UNUSED] RTC periodic interrupt
EXC_RTC_CUI	[UNUSED] RTC carry interrupt
EXC_SCI_ERI	[UNUSED] SCI Error receive
EXC_SCI_RXI	[UNUSED] SCI Receive ready
EXC_SCI_TXI	[UNUSED] SCI Transmit ready
EXC_SCI_TEI	[UNUSED] SCI Transmit error
EXC_WDT_ITI	[POST ] Watchdog timer
EXC_REF_RCMI	[POST ] Memory refresh compare-match interrupt
EXC_REF_ROVI	[POST ] Memory refresh counter overflow interrupt
EXC_UDI	[POST ] Hitachi UDI
EXC_GPIO_GPIOI	[POST ] I/O port interrupt
EXC_DMAC_DMTE0	[POST ] DMAC transfer end (channel 0)
EXC_DMAC_DMTE1	[POST ] DMAC transfer end (channel 1)
EXC_DMAC_DMTE2	[POST ] DMAC transfer end (channel 2)
EXC_DMAC_DMTE3	[POST ] DMAC transfer end (channel 3)
EXC_DMA_DMAE	[POST ] DMAC address error
EXC_SCIF_ERI	[POST ] SCIF Error receive
EXC_SCIF_RXI	[POST ] SCIF Receive ready
EXC_SCIF_BRI	[POST ] SCIF break
EXC_SCIF_TXI	[POST ] SCIF Transmit ready
EXC_DOUBLE_FAULT	[SOFT ] Exception happened in an ISR
EXC_UNHANDLED_EXC	[SOFT ] Exception went unhandled
EXC_TRAP	[TRAP ] Trap

irq_src_t

enum irq_src_t

Interrupt sources.

Interrupt sources at the SH4 level.

Enumerator
IRQ_SRC_RTC
IRQ_SRC_TMU2
IRQ_SRC_TMU1
IRQ_SRC_TMU0
_IRQ_SRC_RESV
IRQ_SRC_SCI1
IRQ_SRC_REF
IRQ_SRC_WDT
IRQ_SRC_HUDI
IRQ_SRC_SCIF
IRQ_SRC_DMAC
IRQ_SRC_GPIO
IRQ_SRC_IRL3
IRQ_SRC_IRL2
IRQ_SRC_IRL1
IRQ_SRC_IRL0

Function Documentation

arch_irq_disable()

static irq_mask_t arch_irq_disable ( void )

inlinestatic

References arch_irq_restore().

Referenced by irq_disable().

arch_irq_enable()

static void arch_irq_enable ( void )

inlinestatic

References arch_irq_restore().

Referenced by irq_enable().

arch_irq_inside_int()

static int arch_irq_inside_int ( void )

inlinestatic

References inside_int.

Referenced by irq_inside_int().

arch_irq_restore()

static void arch_irq_restore ( irq_mask_t old )

inlinestatic

Referenced by arch_irq_disable(), arch_irq_enable(), and irq_restore().

irq_get_priority()

unsigned int irq_get_priority

(

irq_src_t

src

)

Get the priority of a given IRQ source.

This function returns the priority of a given IRQ source.

Parameters

src	The interrupt source whose priority should be set

Returns

The priority of the IRQ source. A value of 0 means the IRQs are masked.

irq_set_priority()

void irq_set_priority	(	irq_src_t	src,
		unsigned int	prio )

Set the priority of a given IRQ source.

This function can be used to set the priority of a given IRQ source.

Parameters

src	The interrupt source whose priority should be set
prio	The priority to set, in the range [0..15], 0 meaning the IRQs from that source are masked.

Variable Documentation

inside_int

int inside_int

extern

Referenced by arch_irq_inside_int().