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Independent SDK for the Sega Dreamcast
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dmac.h
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1/* KallistiOS ##version##
2
3 dmac.h
4 Copyright (C) 2023 Andy Barajas
5
6*/
7
8/** \file dc/dmac.h
9 \brief Macros to access the DMA controller registers.
10 \ingroup system_dmac
11
12 This header provides a set of macros to facilitate checking
13 the values of various DMA channels on the system.
14
15 DMA channel 0 and its registers (DMAC_SAR0, DMAC_DAR0, DMAC_DMATCR0,
16 DMAC_CHCR0) are used by the hardware and not accessible to us but are
17 documented here anyway.
18
19 DMA channel 2 is strictly used to transfer data to the PVR/TA.
20
21 DMA channel 1 & 3 are free to use.
22
23 \author Andy Barajas
24*/
25
26#ifndef __DC_DMAC_H
27#define __DC_DMAC_H
28
29#include <sys/cdefs.h>
30__BEGIN_DECLS
31
32/** \defgroup system_dmac DMA
33 \brief Driver for the SH4's Direct Memory Access
34 Controller
35 \ingroup system
36
37 @{
38*/
39
40#define DMAC_BASE 0xffa00000
41
42/** \name DMA Source Address Registers (SAR0-SAR3)
43
44 These registers designate the source address for DMA transfers.
45 Currently we only support 32-byte boundary addresses.
46
47 @{
48 */
49
50#define DMAC_SAR0 (*((vuint32 *)(DMAC_BASE + 0x00)))
51#define DMAC_SAR1 (*((vuint32 *)(DMAC_BASE + 0x10)))
52#define DMAC_SAR2 (*((vuint32 *)(DMAC_BASE + 0x20)))
53#define DMAC_SAR3 (*((vuint32 *)(DMAC_BASE + 0x30)))
54
55/** @} */
56
57/** \name DMA Destination Address Registers (DAR0-DAR3)
58
59 These registers designate the destination address for DMA transfers.
60 Currently we only support 32-byte boundary addresses.
61
62 @{
63 */
64
65#define DMAC_DAR0 (*((vuint32 *)(DMAC_BASE + 0x04)))
66#define DMAC_DAR1 (*((vuint32 *)(DMAC_BASE + 0x14)))
67#define DMAC_DAR2 (*((vuint32 *)(DMAC_BASE + 0x24)))
68#define DMAC_DAR3 (*((vuint32 *)(DMAC_BASE + 0x34)))
69
70/** @} */
71
72/** \name DMA Transfer Count Registers (DMATCR0-DMATCR3)
73
74 These registers define the transfer count for each DMA channel. The count
75 is defined as: num_bytes_to_transfer/32
76
77 @{
78 */
79
80#define DMAC_DMATCR0 (*((vuint32 *)(DMAC_BASE + 0x08)))
81#define DMAC_DMATCR1 (*((vuint32 *)(DMAC_BASE + 0x18)))
82#define DMAC_DMATCR2 (*((vuint32 *)(DMAC_BASE + 0x28)))
83#define DMAC_DMATCR3 (*((vuint32 *)(DMAC_BASE + 0x38)))
84
85/** @} */
86
87/** \name DMA Channel Control Registers (CHCR0-CHCR3)
88
89 These registers configure the operating mode and transfer methodology for
90 each channel.
91
92 For DMAC_CHCR2, it should always be set to 0x12c1 (source address
93 incremented, burst mode, interrupt disable, DMA enable).
94
95 For DMAC_CHCR1 and DMAC_CHCR3, it would probably be set to 0x1241
96 (source address incremented, cycle steal mode, interrupt disable,
97 DMA enable).
98
99 @{
100 */
101
102#define DMAC_CHCR0 (*((vuint32 *)(DMAC_BASE + 0x0c)))
103#define DMAC_CHCR1 (*((vuint32 *)(DMAC_BASE + 0x1c)))
104#define DMAC_CHCR2 (*((vuint32 *)(DMAC_BASE + 0x2c)))
105#define DMAC_CHCR3 (*((vuint32 *)(DMAC_BASE + 0x3c)))
106
107/** @} */
108
109
110/**
111 \brief A register that dictates the overall operation of the DMAC.
112
113 So far we only use it check the status of DMA operations.
114
115 */
116#define DMAC_DMAOR (*((vuint32 *)(DMAC_BASE + 0x40)))
117
118/** \name List of helpful masks to check operations
119
120 The DMAOR_STATUS_MASK captures the On-Demand Data Transfer Mode (Bit 15),
121 Address Error Flag (Bit 2), NMI Flag (Bit 1), and DMAC Master Enable (Bit 0).
122
123 The DMAOR_NORMAL_OPERATION is a state where DMAC Master Enable is active,
124 and the On-Demand Data Transfer Mode is not set, with no address errors
125 or NMI inputs.
126
127 @{
128*/
129
130#define DMAOR_STATUS_MASK 0x8007
131#define DMAOR_NORMAL_OPERATION 0x8001
132
133/** @} */
134
135/** @} */
136
137__END_DECLS
138
139#endif /* __DC_DMAC_H */
140