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Independent SDK for the Sega Dreamcast
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broadband_adapter.h
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1/* KallistiOS ##version##
2
3 dc/net/broadband_adapter.h
4 Copyright (C) 2001-2002 Megan Potter
5
6*/
7
8/** \file dc/net/broadband_adapter.h
9 \brief Broadband Adapter support.
10 \ingroup bba
11
12 This file contains declarations related to support for the HIT-0400
13 "Broadband Adapter". There's not really anything that users will generally
14 have to deal with in here.
15
16 \author Megan Potter
17*/
18
19#ifndef __DC_NET_BROADBAND_ADAPTER_H
20#define __DC_NET_BROADBAND_ADAPTER_H
21
22#include <sys/cdefs.h>
23__BEGIN_DECLS
24
25/** \defgroup bba Broadband Adapter
26 \brief Driver for the Dreamcast's BBA (RTL8139C).
27 \ingroup networking_drivers
28 @{
29*/
30
31/** \defgroup bba_regs Registers
32 \brief Registers and related info for the broadband adapter
33 @{
34*/
35
36/** \defgroup bba_regs_locs Locations
37 \brief Locations for various broadband adapter registers.
38
39 The default assumption is that these are all RW at any aligned size unless
40 otherwise noted. ex (RW 32bit, RO 16/8) indicates read/write at 32bit and
41 read-only at 16 or 8bits.
42
43 @{
44*/
45#define RT_IDR0 0x00 /**< \brief MAC address 0 (RW 32bit, RO 16/8) */
46#define RT_IDR1 0x01 /**< \brief MAC address 1 (Read-only) */
47#define RT_IDR2 0x02 /**< \brief MAC address 2 (Read-only) */
48#define RT_IDR3 0x03 /**< \brief MAC address 3 (Read-only) */
49#define RT_IDR4 0x04 /**< \brief MAC address 4 (RW 32bit, RO 16/8) */
50#define RT_IDR5 0x05 /**< \brief MAC address 5 (Read-only) */
51#define RT_RES06 0x06 /**< \brief Reserved */
52#define RT_RES07 0x07 /**< \brief Reserved */
53#define RT_MAR0 0x08 /**< \brief Multicast filter 0 (RW 32bit, RO 16/8) */
54#define RT_MAR1 0x09 /**< \brief Multicast filter 1 (Read-only) */
55#define RT_MAR2 0x0A /**< \brief Multicast filter 2 (Read-only) */
56#define RT_MAR3 0x0B /**< \brief Multicast filter 3 (Read-only) */
57#define RT_MAR4 0x0C /**< \brief Multicast filter 4 (RW 32bit, RO 16/8) */
58#define RT_MAR5 0x0D /**< \brief Multicast filter 5 (Read-only) */
59#define RT_MAR6 0x0E /**< \brief Multicast filter 6 (Read-only) */
60#define RT_MAR7 0x0F /**< \brief Multicast filter 7 (Read-only) */
61#define RT_TXSTATUS0 0x10 /**< \brief Transmit status 0 (32bit only) */
62#define RT_TXSTATUS1 0x14 /**< \brief Transmit status 1 (32bit only) */
63#define RT_TXSTATUS2 0x18 /**< \brief Transmit status 2 (32bit only) */
64#define RT_TXSTATUS3 0x1C /**< \brief Transmit status 3 (32bit only) */
65#define RT_TXADDR0 0x20 /**< \brief Tx descriptor 0 (32bit only) */
66#define RT_TXADDR1 0x24 /**< \brief Tx descriptor 1 (32bit only) */
67#define RT_TXADDR2 0x28 /**< \brief Tx descriptor 2 (32bit only) */
68#define RT_TXADDR3 0x2C /**< \brief Tx descriptor 3 (32bit only) */
69#define RT_RXBUF 0x30 /**< \brief Receive buffer start address (32bit only) */
70#define RT_RXEARLYCNT 0x34 /**< \brief Early Rx byte count (RO 16bit) */
71#define RT_RXEARLYSTATUS 0x36 /**< \brief Early Rx status (RO) */
72#define RT_CHIPCMD 0x37 /**< \brief Command register */
73#define RT_RXBUFTAIL 0x38 /**< \brief Current address of packet read (queue tail) (16bit only) */
74#define RT_RXBUFHEAD 0x3A /**< \brief Current buffer address (queue head) (RO 16bit) */
75#define RT_INTRMASK 0x3C /**< \brief Interrupt mask (16bit only) */
76#define RT_INTRSTATUS 0x3E /**< \brief Interrupt status (16bit only) */
77#define RT_TXCONFIG 0x40 /**< \brief Tx config (32bit only) */
78#define RT_RXCONFIG 0x44 /**< \brief Rx config (32bit only) */
79#define RT_TIMER 0x48 /**< \brief A general purpose counter, any write clears (32bit only) */
80#define RT_RXMISSED 0x4C /**< \brief 24 bits valid, write clears (32bit only) */
81#define RT_CFG9346 0x50 /**< \brief 93C46 command register */
82#define RT_CONFIG0 0x51 /**< \brief Configuration reg 0 */
83#define RT_CONFIG1 0x52 /**< \brief Configuration reg 1 */
84#define RT_RES53 0x53 /**< \brief Reserved */
85#define RT_TIMERINT 0x54 /**< \brief Timer interrupt register (32bit only) */
86#define RT_MEDIASTATUS 0x58 /**< \brief Media status register */
87#define RT_CONFIG3 0x59 /**< \brief Config register 3 */
88#define RT_CONFIG4 0x5A /**< \brief Config register 4 */
89#define RT_RES5B 0x5B /**< \brief Reserved */
90#define RT_MULTIINTR 0x5C /**< \brief Multiple interrupt select (32bit only) */
91#define RT_RERID 0x5E /**< \brief PCI Revision ID (10h) (Read-only) */
92#define RT_RES5F 0x5F /**< \brief Reserved */
93#define RT_MII_TSAD 0x60 /**< \brief Transmit status of all descriptors (RO 16bit) */
94#define RT_MII_BMCR 0x62 /**< \brief Basic Mode Control Register (16bit only) */
95#define RT_MII_BMSR 0x64 /**< \brief Basic Mode Status Register (RO 16bit) */
96#define RT_AS_ADVERT 0x66 /**< \brief Auto-negotiation advertisement reg (16bit only) */
97#define RT_AS_LPAR 0x68 /**< \brief Auto-negotiation link partner reg (RO 16bit) */
98#define RT_AS_EXPANSION 0x6A /**< \brief Auto-negotiation expansion reg (RO 16bit) */
99
100#define RT_CONFIG5 0xD8 /**< \brief Config register 5 */
101/** @} */
102
103/** \defgroup bba_regs_fields Fields
104 \brief Register fields for the broadband adapter
105 @{
106*/
107
108/** \defgroup bba_miicb MII Control Bits
109 \brief BBA media independent interface control register fields
110 @{
111*/
112#define RT_MII_RESET 0x8000 /**< \brief Reset the MII chip */
113#define RT_MII_RES4000 0x4000 /**< \brief Reserved */
114#define RT_MII_SPD_SET 0x2000 /**< \brief 1 for 100 0 for 10. Ignored if AN enabled. */
115#define RT_MII_AN_ENABLE 0x1000 /**< \brief Enable auto-negotiation */
116#define RT_MII_RES0800 0x0800 /**< \brief Reserved */
117#define RT_MII_RES0400 0x0400 /**< \brief Reserved */
118#define RT_MII_AN_START 0x0200 /**< \brief Start auto-negotiation */
119#define RT_MII_DUPLEX 0x0100 /**< \brief 1 for full 0 for half. Ignored if AN enabled. */
120/** @} */
121
122/** \defgroup bba_miisb MII Status Bits
123 \brief BBA media independent interface status register fields
124 @{
125*/
126#define RT_MII_LINK 0x0004 /**< \brief Link is present */
127#define RT_MII_AN_CAPABLE 0x0008 /**< \brief Can do auto negotiation */
128#define RT_MII_AN_COMPLETE 0x0020 /**< \brief Auto-negotiation complete */
129#define RT_MII_10_HALF 0x0800 /**< \brief Can do 10Mbit half duplex */
130#define RT_MII_10_FULL 0x1000 /**< \brief Can do 10Mbit full */
131#define RT_MII_100_HALF 0x2000 /**< \brief Can do 100Mbit half */
132#define RT_MII_100_FULL 0x4000 /**< \brief Can do 100Mbit full */
133/** @} */
134
135/** \defgroup bba_cbits Command Bits
136 \brief BBA command register fields
137
138 OR appropriate bit values together and write into the RT_CHIPCMD register to
139 execute the command.
140
141 @{
142*/
143#define RT_CMD_RESET 0x10 /**< \brief Reset the RTL8139C */
144#define RT_CMD_RX_ENABLE 0x08 /**< \brief Enable Rx */
145#define RT_CMD_TX_ENABLE 0x04 /**< \brief Enable Tx */
146#define RT_CMD_RX_BUF_EMPTY 0x01 /**< \brief Empty the Rx buffer */
147/** @} */
148
149/** \defgroup bba_ibits Interrupt Status Bits
150 \brief BBA interrupt status fields
151 @{
152*/
153#define RT_INT_PCIERR 0x8000 /**< \brief PCI Bus error */
154#define RT_INT_TIMEOUT 0x4000 /**< \brief Set when TCTR reaches TimerInt value */
155#define RT_INT_RXFIFO_OVERFLOW 0x0040 /**< \brief Rx FIFO overflow */
156#define RT_INT_RXFIFO_UNDERRUN 0x0020 /**< \brief Packet underrun / link change */
157#define RT_INT_LINK_CHANGE 0x0020 /**< \brief Packet underrun / link change */
158#define RT_INT_RXBUF_OVERFLOW 0x0010 /**< \brief Rx BUFFER overflow */
159#define RT_INT_TX_ERR 0x0008 /**< \brief Tx error */
160#define RT_INT_TX_OK 0x0004 /**< \brief Tx OK */
161#define RT_INT_RX_ERR 0x0002 /**< \brief Rx error */
162#define RT_INT_RX_OK 0x0001 /**< \brief Rx OK */
163
164/** \brief Composite RX bits we check for while doing an RX interrupt. */
165#define RT_INT_RX_ACK (RT_INT_RXFIFO_OVERFLOW | RT_INT_RXBUF_OVERFLOW | RT_INT_RX_OK)
166/** @} */
167
168/** \defgroup bba_tbits RTL8139C Transmit Status Bits
169 \brief BBA transmit status register fields
170 @{
171*/
172#define RT_TX_CARRIER_LOST 0x80000000 /**< \brief Carrier sense lost */
173#define RT_TX_ABORTED 0x40000000 /**< \brief Transmission aborted */
174#define RT_TX_OUT_OF_WINDOW 0x20000000 /**< \brief Out of window collision */
175#define RT_TX_STATUS_OK 0x00008000 /**< \brief Status ok: a good packet was transmitted */
176#define RT_TX_UNDERRUN 0x00004000 /**< \brief Transmit FIFO underrun */
177#define RT_TX_HOST_OWNS 0x00002000 /**< \brief Set to 1 when DMA operation is completed */
178#define RT_TX_SIZE_MASK 0x00001fff /**< \brief Descriptor size mask */
179/** @} */
180
181/** \defgroup bba_rbits Receive Status Bits
182 \brief BBA receive status register fields
183 @{
184*/
185#define RT_RX_MULTICAST 0x8000 /**< \brief Multicast packet */
186#define RT_RX_PAM 0x4000 /**< \brief Physical address matched */
187#define RT_RX_BROADCAST 0x2000 /**< \brief Broadcast address matched */
188#define RT_RX_BAD_SYMBOL 0x0020 /**< \brief Invalid symbol in 100TX packet */
189#define RT_RX_RUNT 0x0010 /**< \brief Packet size is <64 bytes */
190#define RT_RX_TOO_LONG 0x0008 /**< \brief Packet size is >4K bytes */
191#define RT_RX_CRC_ERR 0x0004 /**< \brief CRC error */
192#define RT_RX_FRAME_ALIGN 0x0002 /**< \brief Frame alignment error */
193#define RT_RX_STATUS_OK 0x0001 /**< \brief Status ok: a good packet was received */
194/** @} */
195
196/** \defgroup bba_configrx RTL8139C RX Config Register (RT_RXCONFIG) bits
197
198 From RTL8139C(L) datasheet v1.4.
199
200 @{
201*/
202#define RT_ERTH(n) ((n) <<24) /**< \brief Early RX Threshold multiplier n/16 or 0 for none */
203
204#define RT_RXC_MulERINT 0x00020000 /**< \brief 0 for Early Receive Interrupt only on familiar protocols 1 for any */
205#define RT_RXC_RER8 0x00010000 /**< \brief 1 sets the acceptance of runt error packets */
206#define RT_RXC_RXFTH(n) ((n) <<13) /**< \brief 2^(4+n) bytes from 0-6 (16b - 1Kb) or 7 for none */
207#define RT_RXC_RBLEN(n) ((n) <<11) /**< \brief Set Rx ring buffer len to 16b + 2^(3+n) kb. */
208#define RT_RXC_MXDMA(n) ((n) << 8) /**< \brief 2^(4+n) bytes from 0-6 (16b - 1Kb) or 7 for unlimited */
209
210#define RT_RXC_WRAP 0x00000080 /**< \brief 0 to use wrapping mode or 1 to not (Ignored for 64Kb buffer length) */
211#define RT_RXC_9356SEL 0x00000040 /**< \brief 0 if EEPROM is 9346, 1 if 9356. RO */
212#define RT_RXC_AER 0x00000020 /**< \brief Accept Error Packets */
213#define RT_RXC_AR 0x00000010 /**< \brief Accept Runt (8-64 byte) Packets */
214#define RT_RXC_AB 0x00000008 /**< \brief Accept Broadcast Packets */
215#define RT_RXC_AM 0x00000004 /**< \brief Accept Multicast Packets */
216#define RT_RXC_APM 0x00000002 /**< \brief Accept Physical Match Packets */
217#define RT_RXC_AAP 0x00000001 /**< \brief Accept Physical Address Packets */
218/** @} */
219
220/** \defgroup bba_config1bits RTL8139C Config Register 1 (RT_CONFIG1) Bits
221 \brief BBA config register 1 fields
222
223 From RTL8139C(L) datasheet v1.4
224
225 @{
226*/
227#define RT_CONFIG1_LED1 0x80 /**< \brief XXX DC bba has no LED, maybe repurposed. */
228#define RT_CONFIG1_LED0 0x40 /**< \brief XXX DC bba has no LED, maybe repurposed. */
229#define RT_CONFIG1_DVRLOAD 0x20 /**< \brief Sets the Driver as loaded. */
230#define RT_CONFIG1_LWACT 0x10 /**< \brief LWAKE active mode. Default 0. */
231#define RT_CONFIG1_MEMMAP 0x08 /**< \brief Registers mapped to PCI mem space. Read Only */
232#define RT_CONFIG1_IOMAP 0x04 /**< \brief Registers mapped to PCI I/O space. Read Only */
233#define RT_CONFIG1_VPD 0x02 /**< \brief Enable Vital Product Data. */
234#define RT_CONFIG1_PMEn 0x01 /**< \brief Power Management Enable */
235/** @} */
236
237/** \defgroup bba_config4bits RTL8139C Config Register 4 (RT_CONFIG4) Bits
238 \brief BBA config register 4 fields
239
240 From RTL8139C(L) datasheet v1.4. Only RT_CONFIG4_RxFIFIOAC is used.
241
242 @{
243*/
244#define RT_CONFIG4_RxFIFIOAC 0x80 /**< \brief Auto-clear the Rx FIFO overflow. */
245#define RT_CONFIG4_AnaOff 0x40 /**< \brief Turn off analog power. Default 0. */
246#define RT_CONFIG4_LongWF 0x20 /**< \brief Long Wake-up Frames. */
247#define RT_CONFIG4_LWPME 0x10 /**< \brief LWake vs PMEB. */
248#define RT_CONFIG4_RES08 0x08 /**< \brief Reserved. */
249#define RT_CONFIG4_LWPTN 0x04 /**< \brief LWAKE Pattern. */
250#define RT_CONFIG4_RES02 0x02 /**< \brief Reserved. */
251#define RT_CONFIG4_PBWake 0x01 /**< \brief Disable pre-Boot Wakeup. */
252/** @} */
253
254/** \defgroup bba_config5bits RTL8139C Config Register 5 (RT_CONFIG5) Bits
255 \brief BBA config register 5 fields
256
257 From RTL8139C(L) datasheet v1.4. Only RT_CONFIG5_LDPS is used.
258
259 @{
260*/
261#define RT_CONFIG5_RES80 0x80 /**< \brief Reserved. */
262#define RT_CONFIG5_BWF 0x40 /**< \brief Enable Broadcast Wakeup Frame. Default 0. */
263#define RT_CONFIG5_MWF 0x20 /**< \brief Enable Multicast Wakeup Frame. Default 0. */
264#define RT_CONFIG5_UWF 0x10 /**< \brief Enable Unicast Wakeup Frame. Default 0. */
265#define RT_CONFIG5_FIFOAddr 0x08 /**< \brief Set FIFO address pointer. For testing only. */
266#define RT_CONFIG5_LDPS 0x04 /**< \brief Disable Link Down Power Saving mode. */
267#define RT_CONFIG5_LANW 0x02 /**< \brief Enable LANWake signal. */
268#define RT_CONFIG5_PME_STS 0x01 /**< \brief Allow PCI reset to set PME_Status bit. */
269/** @} */
270
271/** @} */
272
273/** @} */
274
275/** \brief Retrieve the MAC Address of the attached BBA.
276
277 This function reads the MAC Address of the BBA and places it in the buffer
278 passed in. The resulting data is undefined if no BBA is connected.
279
280 \param arr The array to read the MAC into.
281*/
282void bba_get_mac(uint8 *arr);
283
284/** \defgroup bba_rx RX
285 \brief Receive packet API for the BBA
286 @{
287*/
288
289/** \brief Receive packet callback function type.
290
291 When a packet is received by the BBA, the callback function will be called
292 to handle it.
293
294 \param pkt A pointer to the packet in question.
295 \param len The length, in bytes, of the packet.
296*/
297typedef void (*eth_rx_callback_t)(uint8 *pkt, int len);
298
299/** \brief Set the ethernet packet receive callback.
300
301 This function sets the function called when a packet is received by the BBA.
302 Generally, this inputs into the network layer.
303
304 \param cb A pointer to the new callback function.
305*/
306void bba_set_rx_callback(eth_rx_callback_t cb);
307
308/** @} */
309
310/** \defgroup bba_tx TX
311 \brief Transmit packet API for the BBA
312 @{
313*/
314
315/** \defgroup bba_txrv Return Values
316 \brief Return values for bba_tx()
317 @{
318*/
319#define BBA_TX_OK 0 /**< \brief Transmit success */
320#define BBA_TX_ERROR -1 /**< \brief Transmit error */
321#define BBA_TX_AGAIN -2 /**< \brief Retry transmit again */
322/** @} */
323
324/** \defgroup bba_wait Wait Modes
325 \brief Wait modes for bba_tx()
326 @{
327*/
328#define BBA_TX_NOWAIT 0 /**< \brief Don't block waiting for the transfer. */
329#define BBA_TX_WAIT 1 /**< \brief Wait, if needed on transfer. */
330/** @} */
331
332/** \brief Transmit a single packet.
333
334 This function transmits a single packet on the bba, waiting for the link to
335 become stable, if requested.
336
337 \param pkt The packet to transmit.
338 \param len The length of the packet, in bytes.
339 \param wait BBA_TX_WAIT if you don't mind blocking for the
340 all clear to transmit, BBA_TX_NOWAIT otherwise.
341
342 \retval BBA_TX_OK On success.
343 \retval BBA_TX_ERROR If there was an error transmitting the packet.
344 \retval BBA_TX_AGAIN If BBA_TX_NOWAIT was specified and it is not ok to
345 transmit right now.
346*/
347int bba_tx(const uint8 *pkt, int len, int wait);
348
349/** @} */
350
351/* \cond */
352/* Initialize */
353int bba_init(void);
354
355/* Shutdown */
356int bba_shutdown(void);
357/* \endcond */
358
359/** @} */
360
361__END_DECLS
362
363#endif /* __DC_NET_BROADBAND_ADAPTER_H */
364
bba_set_rx_callback
void bba_set_rx_callback(eth_rx_callback_t cb)
Set the ethernet packet receive callback.
eth_rx_callback_t
void(* eth_rx_callback_t)(uint8 *pkt, int len)
Receive packet callback function type.
Definition broadband_adapter.h:297
bba_tx
int bba_tx(const uint8 *pkt, int len, int wait)
Transmit a single packet.
bba_get_mac
void bba_get_mac(uint8 *arr)
Retrieve the MAC Address of the attached BBA.
uint8
unsigned char uint8
8-bit unsigned integer
Definition types.h:35